1. 1 Logic Synthesis Using Cadence Ambit

2. 2 Environment Setup Enter the following to.cshrc or a c-shell command file. –setenv LM_LICENSE_FILE full_path/license.dat –setenv AMBIT_SLIB_PATH.:lib1path:lib2path –set path = (full_path/ambit3.0/BuildGates/v3.0/bin $path) Use the following to setup the NPU environment: % source /export/home/tools/setup/ambit/setup.cmd The tool can be started using the “ac_shell” command. “ac_shell” is similar to Synopsys “dc_shell” command. “ac_shell” commands can be invoked using either the “-f” option or “source command: –% ac_shell –f design.ac –Or ac_shell> source design.ac

3. 3 Getting Help under ac_shell “ac_shell” supports the help command like the “dc_shell”. The help messages are very brief and they do not contain any examples like the dc_shell. One very good feature is that a partial command can be entered, and ac_shell can list all the commands matching the partial words: –ac_shell> set_

4. 4 dc_shell commands translation Most dc_shell commands can be mapped into ac_shell commands. ac_shell does not accept dc_shell commands, however ac_shell can list the corresponding dc_shell commands: –ac_shell> help dc_shell_command

5. 5 Library Compilation Ambit can use Synopsys.lib format directly using the “libcompile” command: –% libcompile npu018.lib npu018.alf “libcompile” runs as a stand alone executable unlike the Synopsys “read_lib” and “write_lib” commands which are supported as dc_shell commands.

6. 6 Setting Library Search Path Technology search path is set from outside the ac_shell environment at the Unix prompt: –% setenv AMBIT_SLIB_PATH.:lib1path:lib2path If the search path is not set, the technology libraries must be read in with full path. The above is equivalent to the functionality of “search_path” command in Synopsys dc_shell.

7. 7 Reading technology libraries The “read_alf” command can be used to read in technology files: –read_alf npu018.alf –read_alf memory1.alf Target technology library can be set using the following: –set_global target_technology {npu018} Multiple target technology libraries can be set using the following: –set_global target_technology {npu018 memory1_lib mem2_lib}

8. 8 Synthesis Directives Like Synopsys, Cadence supports synthesis directives. When Verilog HDL construct can be synthesized into more than one implementations, a directive can be used. Cadence ambit supports the following two styles: –// ambit synthesis –/* ambit synthesis */ The most commonly used synthesis directives are: –case (full, parallel or mux) –architecture (ripple or cla) –FSM (enum, state_vector)

9. 9 Full Case Directive Full case means that the case expression can only evaluate to the values specified by the case labels (expressions). Full case is specified as: –case (exp) // ambit synthesis case = full 4’b000: f = … When the case is “full”, it implies two things: –No latch will be generated. –No default statement is necessary.

10. 10 Parallel Case Directive A parallel case means that all the case branches have the same priority of matching the case expression. Parallel case is specified as: –case (case_exp) // ambit synthesis case = parallel 4’b0000 : f = … When the parallel directive is specified, no priority structure is built.

11. 11 Case Mux Directive Synopsys does not have this case directive. When a case statement has the mux directive, A mux is used in decoding the branches. (I do not have any experience using this option.)

12. 12 Architecture Selection Directive The architecture selection directives are used in arithmetic expressions. The syntax: –// ambit synthesis architecture = cla or ripple Example: –// ambit synthesis architecture = ripple assign s = a + b;

13. 13 FSM Directives There are two FSM directives enum and state_vector. “enum” is used to associate the state variables with the state value parameters: –parameter // ambit synthesis enum state_info S0 = 2’b00, S1 = 2’b10; reg[1:0] /* ambit synthesis enum state_info */ ps; reg[1:0] /* ambit synthesis enum state_info */ ns; “state_vector” is used to specify the state register encoding scheme: –// ambit synthesis state_vector ps –encoding one_hot always @(posedge clk) begin …

14. 14 Reading in Verilog Files Like in dc_shell, Verilog files can be read in individually or as a group of files: –read_verilog design.v –read_verilog [glob submodule*.v] It needs to be noted that, ac_shell does not allow “#” delays in the Verilog source code. They must be removed (for some versions, warnings are generated for other versions).

15. 15 Define Clock Waveform Ambit requires an ideal clock to be defined first with an name, period and waveform: rising edge falling edge –set_clock ideal_clk –period 10 –waveform { 0 5} Clocks in the design can be defined using the set_clock_arrival_time command: –set_clock_arrival_time –rise 0 –fall 5 –clock ideal_clk clkport A clock can be defined directly under dc_shell. Both tools use ideal clock in timing analysis by default.

16. 16 Define Input Constraints The set_data_arrival_time is used to define the relationship of the current chip with respect to the previous one: –set_data_arrival_time 0.0 –clock ideal_clock [find –port –input *] –Arrival time of 0.0 means that there is NO delay by the previous chip. The “-clock” option is not required for a combinational design. Both dc_shell and ac_shell have the same semantics (meaning.)

17. 17 Define Output Constraints Ambit uses data required time to constrain the outputs: –set_data_required_time 10 –clock –ideal_clock [find –port –output *] –The required time refers to the amount of time within the chip. dc_shell uses “set_output_delay” to specify the amount of time for the next chip. The “set_output_delay” equivalent command under Ambit is “set_external_delay”: –set_external_delay 0.0 –clock ideal_clock [find –port –output *]

18. 18 Setting other Constraints transition constraint can be set using slew_time_limit: –set_global slew_time_limit 1.2 (global) –set_slew_time_limit 1.4 {A B C} “set_load” is equivalent to set_port_capacitance_limit: –set_global capacitance_limit 6 –set_port_capacitance_limit 5 {pA pB} Fanout limit can be supported using the following: –set_global fanout_load_limit 12 –set_fanout_load_limit 8 {outportA outportB}

19. 19 Report Area The report_area can be used to report the total area for the current design: –ac_shell> report_area

20. 20 Report Timing The command name for Ambit is also “report_timing”. The equivalent “report_timing –delay max” in dc_shell is “report_timing –late” for ac_shell. The equivalent “report_timing –delay min” in dc_shell is “report_timing –early” for ac_shell. Unlike dc_shell, ac_shell does not report timing path if design constraints are not set.

21. 21 Writing output files The synthesize design can be written in Verilog format: –write_verilog –hier design.vs The timing report file can be re-directed to a report file using the standard Unix “>” and “>>” operators. The SDF file can be written out using the “write_sdf” command: –write_sdf design.sdf

22. 22 Generating SDF Constraint File –Many Placement & Routing tools can import timing constraints from a synthesis tool. –The Constraint file is typically saved in the SDF format. –Ambit can produce a SDF constraint file using the following: write_constraint file_name –Ambit writes the user’s target timing constraint, not the actual path delays of the synthesized design.

23. 23 Sample Script The following is a sample script using two target libraries: –read_alf mem.alf –read_alf nlc18.alf –read_verilog bist_top.v –set_global target_technology {mem nlc18} –do_build_generic –set_top_timing_module func –set_clock clkgrp –period 5.0 –waveform {0 5} –set_clock_arrival_time –clock clkgrp 0.0 {BCLK, MCLK} –set_data_arrival_time 0.0 –clock clkgrp [find –input –no_clock *] –set_external_delay 0.0 –clock clkgrp [find –output *] –do_optimize –report_timing –max_paths 100 –late –report_timing –max_paths 100 –early –report_area –write_verilog –hier design.vs –write_sdf design.sdf

24. 24 Exercise Take an existing design by coping it from the following location: /export/home/tools/npu/ee561/control.v Create a clock with T = 2ns Set both input_delay and output_delay to be zero Synthesize it for using Synopsys report both area and delay Repeat the same for Ambit Compare the results