1. Subcircuits Example subcircuits Each consists of one or more transistors. They are not used by themselves.

2. Subcircuits Switches Diodes/active resistors Current mirrors Current sources/current sinks Current/voltage references Band gap references

3. MOS switches Ideal Switch MOS transistor as a switch

4. Non-idealities in a switch

5. Simple approximation On operation: V G >> V S or V D, V DS small, triode R ON A B Off operation: V GS < V T, cutoff A B Very good off-char

7. Observations: R ON depends on W, L, V G, V T, V DS, etc R ON is nonlinear (depending on signal) Strategies: Use large W and small L to reduce R ON Use large V GS to reduce the effect of signal dependency Use bootstrapping to increase V GS beyond V DD –V SS Use constant V GS Use constant V B so as to have fixed V T Want: R ON small and constant

8. Effects of switch non-idealities Finite ON Resistance –Non-zero charging and discharging time –Limit settling –Limits conversion rate Ideally: instantaneous charging Actually: takes time

9. Signal level dependence of R ON –Different settling behavior at different signal levels –Introduces nonlinearity –Generate higher order harmonics V in : pure sine wave V C1 : has harmonic distortions

10. Finite OFF Current –Leakage of a held voltage –Coupling through the switch –Accumulates with time

11. Clock Feed through

12. EXAMPLE - Switched Capacitor Integrator (slow clock edge) Assume:

13. At t 2 : At t 3 : Once M 2 turns on at t 3, all charge on C 1 is transferred to C 2

14. Between t 3 and t 4 additional charge is transferred to C 1 from the channel capacitance of M 2. At t 4 : Ideal transfer: Total error:

15. Charge injection When switch is turned off suddenly, charges trapped in the channel injected both either D and S side equally. The amount of trapped charges depends on the slope of V G

16. =U slow regime: Hold value error on C L : L

17. In the fast edge regime: Hold voltage error on C L : Study the example in the book

18. Dummy transistor to cancel clock feed through Complete cancellation is difficult. Requires a complementary clock.

19. Use CMOS switches Advantages - 1.) Larger dynamic range. 2.) Lower ON resistance. Disadvantages - 1.) Requires complementary clock. 2.) Requires more area.

20. Voltage doubler for gate overdrive t2t1

21. Constant V GS Bootstrapping  =0 V DD V G =0  =1 V GS ~V DD

22. When  =1: C p : total parasitic capacitance connected to top plate of C 3.

23. PMOS version offon

24. Concept: Switched cap implementation

25. Summary on Switches To reduce R ON –Use large W and small L –Use CMOS instead of NMOS or PMOS –Use large |V GS | To reduce clock feed through –Use cascode –Use dummy transistor To reduce charge injection –Use dummy –Use slow clock edge –Use complementary clock on switch and dummy To improve linearity –Use large |VGS| –Use vin-independent VGS –Use vin-independent VBS (PMOS switch)

26. Diodes And Active Resistors Simple diode connection Voltage divider Extending the dynamic range Parallel MOSFET resistor –Extending the dynamic range Differential resistor –Single MOSFET –Double MOSFET

27. Diode Connection V DS = V GS  Always in saturation If v > V T, i > 0 else i = 0  diode v i VTVT

28. Generally, g m ≈ 10 g mbs ≈ 100 g ds If V BS =0,

29. Voltage Division Equating i D1 to i D2 results in: V DS1 +V DS2 = V DD - V SS Can use different W/L ratio to achieve desired voltage division Use less power than resistive divider

30. Active vs passive resistors RoRo RoRo Suppose V o =(V DD +V SS )/2 g m1 =g m2 =  V EB =10*0.2=2 m R o =1/4m = 250 ohm I o =  /2 *(V EB ) 2 =0.2mA To achieve the same R o, need two 500 ohm resistors. I o =  /(2*500)=2mA, 10 times =2 =0 Consumes 10 times more power

31. Current sources / sinks Current sink Current source I I V V V I

32. Non-ideal current sources / sinks

33. Two critical figures of merit How flat the operating portion is How small the non-operating region is r out and v min For the simple sink on prev slide:

34. Increasing R out

35. Cascode Current Sink

36. Very flat Too large

37. Reduction of V MIN r out ≈ r ds1 *g m2 r ds2 is large which is good But v min = v T +2V ON needs to be reduced

38. Both just saturating But the 2 I REF s must be the same. How?

39. M6 is ¼ the size, it requires 2 times over drive, or 2 times V EB, or 2 time V ON Very flat V MIN is much smaller

40. Alternative method M5 is ¼ the size Again, the 2 I REF s must be the same.

41. V ON ≈ 0.6V Larger W/L ratio can significantly reduce V ON

42. Matching Improved by Adding M3 Why is it better now?

43. Regulated Cascode Current Sink Near triode, V DS3 ↓, i out ↓, V GS4 ↓, V D4 or V G5 ↑, I out ↑.

44. HW: As we pointed out, the circuit on the previous page suffers from a large V min. 1.Modify the circuit to reduce V min without affecting r out. 2.Once you do that, V DS for M1 and M2 are no longer match. Introduce another modification so that the V DS s are matched.

45. =

47. Current Mirrors/Current Amplifiers

49. Simple Current Mirrors Assuming square law model:

50. Simplest example

51. Use of transistor W to control current gains

52. If  C ox and V T matched: If v DS matched: Current gain or mirror gain is controlled by geometric ratio, which can be made quite accurate

53. Sources of Errors Mismatches in W/L ratios –Use large W, L –PLI Mismatches in  C ox –Large area, common centroid, higher order gradient cancellation Mismatches in v DS –Make v DS the same Mismatches in V T –Large area, cancel gradient, same V BS

54.  effect:

55. V T mismatch effect:

56. Sensitivity A systematic way of computing errors. r =

57. Note: common mode errors do not contribute to matching errors, only differential errors do Therefore, can take:

58. Strategies to reduce errors Matching layout –PLI, common centroid, symmetry, gradient,… –Increased area Matching operating conditions –V D, V S, V B, current densities, …  use cascoding to fix V DS Reduce the sensitivies –Use large V GS -V T –Make equivalent small, make g o small,  use cascoding to reduce g o

59. Straightforward layout to achieve mirror ratio of 4: Matching accuracy not good.

60. Will have better matching But: only approximate common centroid no pli can be more compact HW: suggest a better layout for ratio of 4. GGGGGGGGGGSSSSSS

61. Cascoding M1 and M2 are the mirror pair that determines i o. V DS1 and V DS2 matched g o is small

62. Small signal model

64. Wilson Current Mirror g o is small V DS1 and V DS2 not matched

65. Small signal circuit

66. Computation of r out

68. Improved Wilson Current Mirror

69. In the improved Wilson current mirror: What is rout? What is Vmin? The resistance from D2 to GND is 1/gm which is small. Why not connect G2 to a constant bias to increase that impedance? HW:

70. SPICE simulation

71. Regulated Cascode Current Mirror Same as the regulated cascoded curren sink V DS2 is very stable with respect to v o, but not insensitive to I reg change, not necessarily better matching

72. Implementation of I REG using a simple current mirror

73. Applications of current mirrors Common source amplifier: Load for C.S. Amp

74. Common drain amplifier (source follower)

75. Differential input single-ended output gain stage