1. Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ CprE 281: Digital Logic

2. Registers & Counters CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev

3. Administrative Stuff Homework 8 is out It is due on Monday Nov 11, 2013

4. Quick Review

5. A Parade of Flip-Flops

6. A simple memory element with NOT Gates x x x

7. A simple memory element with NAND Gates x x x

8. A simple memory element with NOR Gates x x x

9. Basic Latch

10. A simple memory element with NOR Gates

12. ResetSet

13. Reset SetQ [ Figure 5.3 from the textbook ] A memory element with NOR gates

14. [ Figure 5.3 & 5.4 from the textbook ] Two Different Ways to Draw the Same Circuit

15. Gated SR Latch

16. [ Figure 5.5a from the textbook ] Circuit Diagram for the Gated SR Latch

17. This is the “gate” of the gated latch

18. Circuit Diagram for the Gated SR Latch Notice that these are complements of each other

19. S R Clk Q Q [ Figure 5.6 from the textbook ] Gated SR latch with NAND gates

20. S R Clk Q Q Gated SR latch with NAND gates In this case the “gate” is constructed using NAND gates! Not AND gates.

21. Gated D Latch

22. [ Figure 5.7a from the textbook ] Circuit Diagram for the Gated D Latch

23. Edge-Triggered D Flip-Flops

24. (a) Circuit D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk [ Figure 5.9a from the textbook ] Master-Slave D Flip-Flop

25. D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk Negative-Edge-Triggered Master-Slave D Flip-Flop Positive-Edge-Triggered Master-Slave D Flip-Flop D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk

26. T Flip-Flop

27. [ Figure 5.15a from the textbook ] T Flip-Flop

28. [ Figure 5.15a from the textbook ] T Flip-Flop Positive-edge-triggered D Flip-Flop

29. [ Figure 5.15a from the textbook ] T Flip-Flop What is this?

30. Q Q T D

31. Q Q T D += ?

32. T 0 1 D Q Q Clock T Flip-Flop

33. What is this? += ?

34. T D Q Q Clock T Flip-Flop

35. JK Flip-Flop

36. [ Figure 5.16a from the textbook ] JK Flip-Flop D = JQ + KQ

37. [ Figure 5.16 from the textbook ] JK Flip-Flop JQ Q K 0 1 Qt1+  Qt  0 (b) Truth table(c) Graphical symbol J 0 0 0 1 1 1 Qt  1 K D Q Q Q Q J Clock (a) Circuit K

38. JK Flip-Flop (How it Works) A versatile circuit that can be used both as a SR flip-flop and as a T flip flop If J=0 and S =0 it stays in the same state Just like SR It can be set and reset J=S and K=R If J=K=1 then it behaves as a T flip-flop

39. Registers

40. Register (Definition) An n-bit structure consisting of flip-flops

41. A simple shift register [ Figure 5.17 from the textbook ]

42. Parallel-access shift register [ Figure 5.18 from the textbook ]

43. Counters

44. A three-bit up-counter [ Figure 5.19 from the textbook ]

45. A three-bit up-counter [ Figure 5.19 from the textbook ] T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 (a) Circuit Clock Q 0 Q 1 Q 2 Count012345670 (b) Timing diagram

46. A three-bit down-counter [ Figure 5.20 from the textbook ]

47. A three-bit down-counter [ Figure 5.20 from the textbook ] T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 (a) Circuit Clock Q 0 Q 1 Q 2 Count076543210 (b) Timing diagram

48. Synchronous Counters

49. A four-bit synchronous up-counter [ Figure 5.21 from the textbook ]

50. A four-bit synchronous up-counter [ Figure 5.21 from the textbook ]

51. Derivation of the synchronous up-counter [ Table 5.1 from the textbook ] 0 0 1 1 0 1 0 1 0 1 2 3 0 0 1 0 1 0 4 5 6 117 0 0 0 0 1 1 1 1 Clock cycle 0080 Q 2 Q 1 Q 0 Q 1 changes Q 2

52. A four-bit synchronous up-counter [ Figure 5.21 from the textbook ]

53. Inclusion of Enable and Clear capability [ Figure 5.22 from the textbook ] T Q Q Clock T Q Q Enable Clear_n T Q Q T Q Q

54. Questions?

55. THE END