1. OIF Electrical Interfaces SXI-5 and TFI-5 Tom Palkert Applied Micro Circuits Corporation (AMCC)

2. SERDES Framer Interface (SFI) FEC Data Clock Data Clock OR OIF Electrical Specifications Status Link Layer NP ATM SAR System Packet Interface (SPI) Data Status Data T D M Switch Fabric PHY Device TDM Fabric to Framer Interface (TFI) Clock SERDES Framer Interface (SFI) Optical Interface (VSR) SERDES Device and Optics Data Clock Data Clock SxI

3. Common Electrical Specification For SFI-5; SPI-5; and TFI-5* * TFI-5 optimized for backplane applications

4. SERDES Framer Interface (SFI) FEC Data Clock Data Clock OR SERDES Framer Interface (SFI) Data Clock Data Clock Optical Interface SERDES Device and Optics SxI-5 Common Electrical Interface Status Transmit Link Layer Device Receive Link Layer Device System Packet Interface (SPI) Data Status Data T F I PHY Device TDM Fabric to Framer Interface (TFI) SxI-5

5. SxI-5 Common Electrical Interface TXREFCK RXREFCK SerdesFramer FEC Processor TXDCK TXDATA [15:0] TXCKSRC TXDCK TXDATA [15:0] TXCKSRC RXREFCK D C A B DC AB RXDCK RXDATA [15:0] RXDSC RXS AB RXDCK RXDATA [15:0] RXDSC RXS A B Deskew signal aligns data channels TXDSC S y s t e m t o O p t i c s O p t i c s t o S y s t e m

6. SxI-5 Common Electrical Interface Data Status Data Status System Packet Interface (SPI-5) Transmit Interface (SPI-5) Receive Interface (SPI-5) SERDES Framer Interface (SFI-5) SERDES Framer Interface (SFI-5) Data Clock Transmit Link Layer Device Receive Link Layer Device SERDES Device and Optics FEC Device PHY Device Provide well defined voltage levels and timing budgets

7. SxI-5 Common Electrical Interface Data Status Data Status System Packet Interface (SPI-5) Transmit Interface (SPI-5) Receive Interface (SPI-5) SERDES Framer Interface (SFI-5) SERDES Framer Interface (SFI-5) Data Clock Transmit Link Layer Device Receive Link Layer Device SERDES Device and Optics FEC Device PHY Device Capable of driving at least 8 inches of FR4 with 1 or 2 connectors 8"

8. SxI-5 Common Electrical Interface Jitter : Phase variations in a signal (clock or data). Complement True Ideal 0-crossing point Sampling point Ideal 1-crossing point Total Jitter is composed of both deterministic and random content.

9. SxI-5 Common Electrical Interface The transmit eye mask specifies the jitter at reference points A and C Normalized bit time [UI] 0XT1XT2 1-XT21-XT11 0 -YT2 -YT1 YT1 YT2 Serdes FEC Processor TXDATA D RXDATA B Differential signal amplitude [V] C A

10. SxI-5 Common Electrical Interface The receive eye mask specifies the jitter at reference points B and D Normalized bit time [UI] 0 1 0 -YR2 -YR1 YR1 YR2 XR1XR2 1-XR21-XR1 Serdes FEC Processor TXDATA C RXDATA A Differential signal amplitude [V] D B

11. SxI-5 Common Electrical Interface Wander: The variation in the phase of a signal (clock or data) after filtering with a low pass filter. Relative Wander between lanes x and y Peak to Peak Skew between lanes x and y Lane X Lane Y Skew: The constant portion of the difference in the arrival time between two signals.

12. TFI-5 TDM Fabric to Framer Interface

13. Reference Diagram

14. TFI-5 Requirements  Support SONET/SDH framers with line-side interfaces of OC-48/STM-16, OC-192/STM-64, and OC- 768/STM-256 and multi-channel framers with lower rate line-side interfaces with an aggregate bandwidth of N x OC-48/STM-16. (e.g. quad OC-12/STM-4).  Support G.709 OTN framers and 10GE LAN/WAN PHY framers by mapping into a SONET/SDH frame  Uses scrambling to ensure transition density.  Support lane bandwidths of 2.488 Gb/s (STS-48) or optionally 3.1104 Gbps (STS-60).  Support de-skew between TFI-5 lanes originating from multiple framers or fabric devices.  Support STS-1 Switching fabrics constructed from multiple devices.  TFI-5 device shall be capable of checking for errors.  Capable of driving at least 30 inches of PCB with 2 connectors for intra-shelf environments and at least 100 meters over optics for inter-shelf environments.  Support DC coupling. AC coupling is optional.  Provide a clear forward migration path to future fabrication processes.  Wide availability of components.

15. TFI-5 Signal Definitions Signal NameFunction TFIDATA The TFI-5 Data (TFIDATA) signal carries the data between the Framer and the Switch Fabric. The same signal definition is applicable to data transfer in the Framer to Fabric direction, and the Fabric to Framer direction. TFIREFCK The TFI-5 Reference Clock (TFIREFCK) signal provides timing reference to all the TFI-5 data (TFIDATA) signals in a system. TFI8KREF The TFI-5 8kHz Frame Reference (TFI8KREF) signal provides reference to frame boundaries for all the devices in a TFI-5 system.

16. TFI-5 Layered approach

17. TFI-5 System Model detailing extent of Layers

18. TFI-5 Frame Format