2. Chapter 10 Memories Boonchuay Supmonchai Integrated Design Application Research (IDAR) Laboratory August 7, 2005

3. B.Supmonchai 2102-545 Digital ICs Memories 2 Outlines  Memory Classification  ROM, SRAM, DRAM, CAM  Memory Architecture  Memory Core Circuits  Periphery Circuits  Reliability  Case Studies

4. B.Supmonchai 2102-545 Digital ICs Memories 3 Review: Basic Building Blocks  Datapath  Execution units  Adder, multiplier, divider, shifter, etc.  Register file and pipeline registers  Multiplexers, decoders  Control  Finite state machines (PLA, ROM, random logic)  Interconnect  Switches, arbiters, buses  Memory  Caches (SRAMs), TLBs, DRAMs, buffers

5. B.Supmonchai 2102-545 Digital ICs Memories 4 Main Memory (DRAM) eDRAM Main Board Second Level Cache (SRAM) CPU Board Secondary Memory (Disk) Control Datapath On-Chip Components RegFile DataCache Instr Cache ITLB DTLB Speed (ns) Speed (ns).1’s 1’s 10’s 100’s 1,000’s Size (bytes) Size (bytes) 100’s K’s 10K’s M’s T’s A Typical Memory Hierarchy principle of locality  By taking advantage of the principle of locality:  Present the user with as much memory as is available in the cheapest technology.  Provide access at the speed offered by the fastest technology. highest lowest highest lowestCost

6. B.Supmonchai 2102-545 Digital ICs Memories 5 Semiconductor Memories Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access SRAM (cache, register file) DRAM FIFO LIFO Shift Register CAM EPROM E 2 PROM FLASH Mask- programmed Electrically- programmed (PROM) 50% of the transistors in a microprocessor are in the memory (reg file, caches, etc.)

7. B.Supmonchai 2102-545 Digital ICs Memories 6 Memory Timing Definitions Read Read Cycle Read Access Write Cycle WriteSetup Data Valid Write Hold Read Access Data Written Write Data

8. B.Supmonchai 2102-545 Digital ICs Memories 7 1D-Memory Architecture: Decoders Too many select signals: N words  N select signals Decoder reduces #s of select signals N words  K (= log 2 N) select signals Word 0 Word 1 Word 2 WordN - 2 WordN - 1 Storage cell M bits S0S0 Input-Output (M bits) S1S1 S2S2 S N-2 S N-1 N words M bits A 0 A 1 A K-1 K = log 2 N Word 0 Word 1 Word 2 WordN - 2 WordN - 1 Storage cell Input-Output (M bits) S0S0 Decoder

9. B.Supmonchai 2102-545 Digital ICs Memories 8 2D-Memory Architecture: Array-Based 1D-architecture suffers from the ASPECT RATIO problem (HEIGHT >> WIDTH) Amplify swing to rail-to-rail amplitude rail-to-rail amplitude Amplify swing to rail-to-rail amplitude rail-to-rail amplitude Select appropriate word Still too slow for bigger memories (> 256K) because the word and bit lines are too long.

10. B.Supmonchai 2102-545 Digital ICs Memories 9 3D-Memory Architecture: Hierarchical Advantages: 1. Shorter word and/or bit lines 2. Block address activates only 1 block saving power 2. Block address activates only 1 block saving power -

11. B.Supmonchai 2102-545 Digital ICs Memories 10 Contents-Addressable Memory (CAM) Data (64 bits) Comparand CAM Array Mask Control Logic R/W Address (9 bits) I/O Buffers Priority Encoder 2 9 Validity Bits Address Decoder 2 9 word x 64 bits Commands

12. B.Supmonchai 2102-545 Digital ICs Memories 11 CAM Operations ReadWriteMatch  3 Modes of CAM Operation: Read, Write, and Match Match  In Match mode, the data are compared to the content in the memories to locate where the data are kept, i.e. its address.  The Comparand keeps the data pattern to match and the Mask indicates which bits are significant.  All 512 rows of the CAM array then simultaneously compare the significant bits of the comparand with the data contained in that row.  Validity bits are set for the rows that contain matched pattern.  If there are more than one matched row, the Row address of the CAM array is used to break the tie.  “Match Found” bit is set if there is a match.

13. B.Supmonchai 2102-545 Digital ICs Memories 12 Read-Only Memory (ROM) Cells WL BL“1” WL BL “0” Diode ROM WL BL WL BL V DD MOS ROM 1 WL BL WL BL GND MOS ROM 2 No isolation More area and higher drive strength

14. B.Supmonchai 2102-545 Digital ICs Memories 13 MOS OR ROM Implementation Shared to reduce overhead Mirror Cell

15. B.Supmonchai 2102-545 Digital ICs Memories 14 MOS NOR ROM Implementation Missing NMOS means storing a “1”

16. B.Supmonchai 2102-545 Digital ICs Memories 15 MOS NOR ROM Layout Polysilicon Metal1 Diffusion Metal1 on Diffusion BL[0]BL[1]BL[2]BL[3] WL[0] WL[1] WL[2] WL[3] GND ACTIVE Layer (9.5 x 7 ) BL[0]BL[1]BL[2]BL[3] WL[0] WL[1] WL[2] WL[3] GND CONTACT Layer (11 x 7 )

17. B.Supmonchai 2102-545 Digital ICs Memories 16 WL[0] WL[1] WL[2] WL[3] V DD Pull-up devices BL[3]BL[2]BL[1]BL[0] MOS NAND ROM All word lines high by default with exception of selected row No Supply or GND needed in the cell

18. B.Supmonchai 2102-545 Digital ICs Memories 17 MOS NAND ROM Layout Using Implantation (5 x 6 ) BL[0]BL[1]BL[2]BL[3] WL[0] WL[1] WL[2] WL[3] Polysilicon Threshold-Altering Implant Diffusion Metal1 on Diffusion METAL-1 Layer (8 x 7 ) BL[0]BL[1]BL[2]BL[3] WL[0] WL[1] WL[2] WL[3] Drastically reduced cell size but Loss in Performance compared to NOR ROM

19. B.Supmonchai 2102-545 Digital ICs Memories 18 Transient Model for NOR ROM Transient Response  time from word line activation to bit line traversing voltage swing (typically 10% of V dd ). Word line parasitics (polysilicon)  Wire resistance  Wire capacitance  Gate capacitance Word line parasitics (polysilicon)  Wire resistance  Wire capacitance  Gate capacitance Bit line parasitics (Metal1)  Wire resistance (negligible)  Wire capacitance  Drain capacitance Bit line parasitics (Metal1)  Wire resistance (negligible)  Wire capacitance  Drain capacitanceVDD C bit r word c word WL BL Metal1 Poly

20. B.Supmonchai 2102-545 Digital ICs Memories 19 Transient Model for NAND ROM VDD C L r word c word WL BL c bit bit r Word line parasitics (polysilicon)  Wire resistance  Wire capacitance  Gate capacitance Word line parasitics (polysilicon)  Wire resistance  Wire capacitance  Gate capacitance Bit line parasitics (Metal1)  Resistance of cascaded transistors dominates  Drain/Source and complete gate capacitance Bit line parasitics (Metal1)  Resistance of cascaded transistors dominates  Drain/Source and complete gate capacitance Worst case scenario: when the cascade chain is populated  distributed RC model

21. B.Supmonchai 2102-545 Digital ICs Memories 20 Example: 512  512 NOR ROM rcM  Word line delay can be computed using the distributed rc-line model where the line consists of M sections/cells.  Assume a (0.5/0.25) pull-up device and a (1.3125/0.25) pull-down transistor t word = 0.38(r word c word )M 2 = 0.38(17.5 Ω * (0.049 + 0.75)fF) * 512 2 = 1.4 ns C bit = 512*(0.8+0.09)fF = 0.46 pF C bit = 512*(0.8+0.09)fF = 0.46 pF t bit, HL = 0.69(13 kΩ /2 || 31 kΩ /5.25)*0.46 pF = 0.98 ns t bit, LH = 0.69(31 kΩ /5.25)*0.46 pF = 1.87 ns  Bit line response time depends on the transition direction.

22. B.Supmonchai 2102-545 Digital ICs Memories 21 Example: 512  512 NAND ROM  Using similar technique, word line delay of the NAND ROM can be computed as  For the bit line, the worst case high-to-low delay occurs when the complete column is populated with 0s except the bottommost transistor. By the distributed rc-line model (which is a fair approximation) t word = 0.38(15 Ω * (0.049 + 0.56)fF) * 512 2 = 1.3 ns t bit, LH = 0.69(31 kΩ /0.0077) * (511*0.85 fF) = 1.2 µs - slow! t bit, HL = 0.38(8.7 kΩ * 0.85 fF) * 511 2 = 0.73 µs  Using Elmore delay for the low-to-high worst case delay which occurs when the bottommost transistor is off.

23. B.Supmonchai 2102-545 Digital ICs Memories 22 NOR and NAND ROM Disadvantages  NOR and NAND ROM inherit all disadvantages of the pseudo-NMOS gate:  Ratioed Logic  Ratioed Logic: VOL is determined by the ratio of the pull-up and pull-down devices -> unacceptable transistor ratios.  Static Power Consumption  Static Power Consumption: static current exists between the supply rails when the output is low -> severe power dissipation  Solution: use fully complimentary NAND and NOR gate (i.e. CMOS)  large number of transistor -> large area

24. B.Supmonchai 2102-545 Digital ICs Memories 23 Precharged MOS NOR ROM pre f WL[0] GND BL[0] WL[1] WL[2] WL[3] BL[1] Precharge devices BL[2]BL[3] GND DD V Can be made as large as necessary, but clock driver becomes harder to design.

25. B.Supmonchai 2102-545 Digital ICs Memories 24 Precharged ROM Advantages  Eliminates the static power dissipation and the ratioed logic requirements with the same cell complexity.  Eliminate the enabling NMOS transistor at the bottom of the pull-down network.  Enables independent control of the pull-up and pull-down timing. dynamic precharging  Almost all of the large memories currently designed, including NVRWM and RAMS, use dynamic precharging.

26. B.Supmonchai 2102-545 Digital ICs Memories 25  Drive the word line from both sides  Use a metal bypass  Use Silicides polysilicon word line metal word line driverdriverWL Reduce delay by 4 polysilicon word line metal bypass WL metal word line K cells Decreasing Word Line Delay

27. B.Supmonchai 2102-545 Digital ICs Memories 26 Decreasing Bit Line Delay (Energy)  Reduce the bit line voltage swing (typical value ~ 0.5 V)  need sense amp for each column to sense/restore signal pulsed word line  Isolate memory cells from the bit lines after sensing (to prevent the cells from changing the bit line voltage further) - pulsed word line  generation of word line pulses very critical  too short  too short - sense amp operation may fail  too long  too long - power efficiency degraded (because bit line swing size depends on duration of the word line pulse)  use feedback signal from bit lines bit line isolation  Isolate sense amps from bit lines after sensing (to prevent bit lines from having large voltage swings) - bit line isolation

28. B.Supmonchai 2102-545 Digital ICs Memories 27 ROM Perspectives  Application-Specific ROMs  Application-Specific ROMs - custom designed for a particular application  Designer has freedom to choose any mask layer (or combination thereof) to program the device.  Commodity ROMs  Commodity ROMs - mass-produced memories that later customized according to customer specifications.  Mask-programmable  Mask-programmable: use contact/metal mask to program the memory; becoming unpopular  Electrically programmable  Electrically programmable: use fuses/anti-fuses to program; “write once” (cannot be reprogrammed).

29. B.Supmonchai 2102-545 Digital ICs Memories 28 Non-Volatile Memories (NVM) Basics Schematic symbol G S D The Floating-gate Avalanche-injection MOS transistor (FAMOS) (FAMOS) Device cross-section Floating gate Source Substrate Gate Drain n + n +_ p t ox t Allow threshold voltage to be altered electrically and retained indefinitely.

30. B.Supmonchai 2102-545 Digital ICs Memories 29 20 V 10 V5 V 20 V DS Avalanche injection Floating-Gate Transistor Programming 0 V - 5 V 0 V DS Removing programming voltage leaves charge trapped 5 V - 2.5 V 5 V DS Programming results in higherV T. V T V T ~ 7V

31. B.Supmonchai 2102-545 Digital ICs Memories 30 Note on NVMs  NVM structure is identical to the ROM except that it uses FAMOS transistors or similar devices at the cell level instead. method of erasing  The method of erasing is the main differentiating factor between the classes of NVM  The programming of the NVM slower  Is typically an order of magnitude slower than the reading operation. no less than twice  Requires high voltage power supply - no less than twice the supply voltage need in the reading operation

32. B.Supmonchai 2102-545 Digital ICs Memories 31 EPROM Summary  Based on ROM structure and FAMOS devices. simple and dense  Extremely simple and dense: suitable for large low-cost memories that do not require regular programming.  Erased by shining UV lights through a transparent window in the package.  UV makes oxide slightly conductive, leaking charges very slowly from the floating gate.

33. B.Supmonchai 2102-545 Digital ICs Memories 32 EPROM Drawbacks slow  Erasure process is slow from 10’s to 1000’s sec and must be done “Off System”.  Limited Endurance  Limited Endurance: Number of erase/program cycles is generally limited to at most 1000.  Reliability Problems  Reliability Problems: device threshold might vary with repeated programming.  Use on-chip circuitry to control the threshold voltage to within an acceptable range during programming.  High power dissipation  High power dissipation during programming.

34. B.Supmonchai 2102-545 Digital ICs Memories 33 EEPROM: FLOTOX Device FLOTOX cross section Fowler-Nordheim I-V characteristic Floating gate Source Substrate p Gate Drain n 1 n 1 20–30 nm 10 nm -10 V 10 V I V GD The FLOating-gate Tunneling OXide (FLOTOX) transistor Injecting electrons onto the gate raises V T. Reverse operation (voltage) lower V T BidirectionalProgramming

35. B.Supmonchai 2102-545 Digital ICs Memories 34 EEPROM Cell WL BL V DD  hard.  Absolute threshold control for FLOTOX transistor is hard.   Over-erasing programmed transistor might end up with a depletion device.  FLOTOX always ON  2 transistor cell  Solution: 2 transistor cell  Write FLOTOX  Read NMOS FLOTOX NMOS

36. B.Supmonchai 2102-545 Digital ICs Memories 35 EEPROM Summary  Larger Area  Larger Area than EPROM of the same capacity  FLOTOX is inherently larger than FAMOS  2T cells as to 1T cell for the EPROM.  Thin oxide is hard to fabricate and expensive. higher  Cost/bit is higher than the EPROMs  Higher versatility:  Higher versatility: in situ programming/erasure  Last longer V T  Last longer (up to 10 5 erase/program cycles) but repeated programming can cause V T to drift due to permanently trapped charges in SiO 2

37. B.Supmonchai 2102-545 Digital ICs Memories 36 Flash EEPROM: ETOX Device Control gate erasure p-substrate Floating gate Thin tunneling oxide n 1 source n 1 drain programming Many other options …

38. B.Supmonchai 2102-545 Digital ICs Memories 37 EPROM Flash Courtesy Intel Cross-sections of NVM cells

39. B.Supmonchai 2102-545 Digital ICs Memories 38 Erase in a NOR Flash Memory

40. B.Supmonchai 2102-545 Digital ICs Memories 39 Write in a NOR Flash Memory

41. B.Supmonchai 2102-545 Digital ICs Memories 40 Read in a NOR Flash Memory

42. B.Supmonchai 2102-545 Digital ICs Memories 41 NAND Flash Memory Unit Cell Word line(poly) Source line (Diff. Layer)

43. B.Supmonchai 2102-545 Digital ICs Memories 42 Word linesSelect transistor Bit line contactSource line contact Active area STI Courtesy Toshiba NAND Flash Memory

44. B.Supmonchai 2102-545 Digital ICs Memories 43 State-of-the-art NVM

45. B.Supmonchai 2102-545 Digital ICs Memories 44  STATIC (SRAM)  DYNAMIC (DRAM) Read-Write Memories (RAM)  Data stored as long as supply is applied  Large (6 transistors/cell)  Fast  Differential  Periodic refresh required  Small (1-3 transistors/cell)  Slower  Single Ended

46. B.Supmonchai 2102-545 Digital ICs Memories 45 6-Transistor CMOS SRAM Cell WL BL V DD M 5 M 6 M 4 M 1 M 2 M 3 BL Q Q

47. B.Supmonchai 2102-545 Digital ICs Memories 46 CMOS SRAM Analysis (Read) WL BL V DD M 5 M 6 M 4 M 1 V V V BL Q = 1 Q = 0 C bit C

48. B.Supmonchai 2102-545 Digital ICs Memories 47 CMOS SRAM Analysis (Read) 0 0 0.2 0.4 0.6 0.8 1 1.2 0.511.21.52 Cell Ratio (CR) 2.53 Voltage Rise (V)

49. B.Supmonchai 2102-545 Digital ICs Memories 48 CMOS SRAM Analysis (Write) BL = 1 = 0 Q = 0 Q = 1 M 1 M 4 M 5 M 6 V DD V WL

50. B.Supmonchai 2102-545 Digital ICs Memories 49 CMOS SRAM Analysis (Write)

51. B.Supmonchai 2102-545 Digital ICs Memories 50 V DD GND Q Q WL BL M1 M3 M4M2 M5M6 6T-SRAM Layout

52. B.Supmonchai 2102-545 Digital ICs Memories 51 Resistance-load SRAM Cell Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem M 3 R L R L V DD WL QQ M 1 M 2 M 4 BL

53. B.Supmonchai 2102-545 Digital ICs Memories 52 SRAM Characteristics

54. B.Supmonchai 2102-545 Digital ICs Memories 53 3-Transistor DRAM Cell No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V WWL -V Tn WWL BL1 M 1 X M 3 M 2 C S 2 RWL V DD V 2 V T D V V 2 V T BL2 1 X RWL WWL

55. B.Supmonchai 2102-545 Digital ICs Memories 54 BL2BL1GND RWL WWL M3 M2 M1 3T-DRAM Layout

56. B.Supmonchai 2102-545 Digital ICs Memories 55 1-Transistor DRAM Cell Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance Voltage swing is small; typically around 250 mV.  V BL V PRE –V BIT V PRE – C S C S C BL + ------------ == V

57. B.Supmonchai 2102-545 Digital ICs Memories 56 DRAM Cell Observations  1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out.  DRAM memory cells are single ended in contrast to SRAM cells.  The read-out of the 1T DRAM cell is destructive  read and refresh operations are necessary for correct operation.  Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.

58. B.Supmonchai 2102-545 Digital ICs Memories 57 DRAM Cell Observations II  When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD

59. B.Supmonchai 2102-545 Digital ICs Memories 58 Sense Amp Operation D V(1) V V(0) t V PRE V BL Sense amp activated Word line activated

60. B.Supmonchai 2102-545 Digital ICs Memories 59 1-T DRAM Cell Uses Polysilicon-Diffusion Capacitance Expensive in Area Cross-section Layout M 1 word line Diffused bit line Polysilicon gate Polysilicon plate Capacitor Metal word line Poly SiO 2 Field Oxide n + n + Inversion layer induced by plate bias Poly

61. B.Supmonchai 2102-545 Digital ICs Memories 60 SEM of poly-diffusion capacitor 1T-DRAM 1T-DRAM SEM

62. B.Supmonchai 2102-545 Digital ICs Memories 61 Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Trench Cell Stacked-capacitor Cell Capacitor dielectric layer Cell plate Word line Insulating Layer IsolationTransfer gate Storage electrode Advanced 1T DRAM Cells

63. B.Supmonchai 2102-545 Digital ICs Memories 62 Static CAM Memory Cell

64. B.Supmonchai 2102-545 Digital ICs Memories 63 CAM in Cache Memory

65. B.Supmonchai 2102-545 Digital ICs Memories 64 Periphery  Decoders  Sense Amplifiers  Input/Output Buffers  Control/Timing Circuitry

66. B.Supmonchai 2102-545 Digital ICs Memories 65 Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder Row Decoders

67. B.Supmonchai 2102-545 Digital ICs Memories 66 Hierarchical Decoders A 2 A 2 A 2 A 3 WL 0 A 2 A 3 A 2 A 3 A 2 A 3 A 3 A 3 A 0 A 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 1 A 1 1 Multi-stage implementation improves performance NAND decoder using 2-input pre-decoders

68. B.Supmonchai 2102-545 Digital ICs Memories 67 2-input NOR decoder2-input NAND decoder Dynamic Decoders

69. B.Supmonchai 2102-545 Digital ICs Memories 68 Advantages: speed (t pd does not add to overall memory access time) Only one extra transistor in signal path Only one extra transistor in signal path Disadvantage: Large transistor count 2-input NOR decoder A 0 S 0 BL 0 1 2 3 A 1 S 1 S 2 S 3 D 4-Input PT Based Column Decoder

70. B.Supmonchai 2102-545 Digital ICs Memories 69 4-to-1 Tree Based Column Decoder Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders buffers progressive sizing combination of tree and pass transistor approaches Solutions: BL 0 1 2 3 D A 0 A 0 A 1 A 1

71. B.Supmonchai 2102-545 Digital ICs Memories 70 t p C  V  I av ----------------= make  V as small as possible smalllarge Idea: Use Sense Amplifer output input s.a. small transition Sense Amplifiers

72. B.Supmonchai 2102-545 Digital ICs Memories 71 Differential Sense Amplifier M 4 M 1 M 5 M 3 M 2 V DD bit SE Out y Directly applicable to SRAMs

73. B.Supmonchai 2102-545 Digital ICs Memories 72 Differential Sensing - SRAM

74. B.Supmonchai 2102-545 Digital ICs Memories 73 Latch-Based Sense Amplifier (DRAM) EQ V DD BL SE  Initialized in its meta- stable point with EQ  Once adequate voltage gap created, sense amp enabled with SE  Positive feedback quickly forces output to a stable operating point.

75. B.Supmonchai 2102-545 Digital ICs Memories 74 Case Studies  Programmable Logic Array  SRAM  Flash Memory

76. B.Supmonchai 2102-545 Digital ICs Memories 75 Programmable Logic Array (PLA)  Structured approach to random logic  “Two level logic implementation”  NOR-NOR (Product of Sums)  NAND-NAND (Sum of Products)  Circuit structure similar to ROM with main difference:  ROM: fully populated  PLA: one element per min term  Importance of PLA has drastically reduced  Slow  Better optimization techniques (Multi-level logic synthesis)

77. B.Supmonchai 2102-545 Digital ICs Memories 76 Pseudo-NMOS PLA AND-planeOR-plane

78. B.Supmonchai 2102-545 Digital ICs Memories 77 Dynamic PLA AND-planeOR-plane GND V DD V X 0 X 0 X 1 f 0 f 1 X 1 X 2 X 2 AND f f OR f f

79. B.Supmonchai 2102-545 Digital ICs Memories 78 (a) Clock signals(b) Timing generation circuitry f t pre t eval f AND f f f f OR f Dummy AND row Clock Signal Generation for self-timed dynamic PLA Dynamic PLA: Clock Signal Generation

80. B.Supmonchai 2102-545 Digital ICs Memories 79 PLA Layout

81. B.Supmonchai 2102-545 Digital ICs Memories 80 4 Megabit SRAM Hierarchical Word-line Architecture

82. B.Supmonchai 2102-545 Digital ICs Memories 81 Bit-line Circuitry

83. B.Supmonchai 2102-545 Digital ICs Memories 82 Sense Amplifier (and Waveforms) I/O Lines Address Data-cut ATD BEQ SEQ DATA Vdd GND SA, SA Vdd GND

84. B.Supmonchai 2102-545 Digital ICs Memories 83 1 Gigabit Flash Memory From [Nakamura02]

85. B.Supmonchai 2102-545 Digital ICs Memories 84 Writing Flash Memory Read level (4.5 V) Number of cells 10 0 0V1V2V Vt of memory cells 3V4V 10 2 4 6 8 Evolution of thresholdsFinal Distribution From [Nakamura02]

86. B.Supmonchai 2102-545 Digital ICs Memories 85 125mm 2 1Gbit NAND Flash Memory 10.7mm 11.7mm 2kB Page buffer & cacheCharge pump 16896 bit lines 32 word lines x 1024 blocks From [Nakamura02]

87. B.Supmonchai 2102-545 Digital ICs Memories 86 125mm 2 1Gbit NAND Flash Memory Technology: Technology: 0.13  m p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al Cell size: Cell size: 0.077  m2 Chip size: Chip size: 125.2mm2 Organization: Organization: 2112 x 8b x 64 page x 1k block Power supply: Power supply: 2.7V-3.6V Cycle time: Cycle time: 50ns Read time: Read time:25  s Program time: Program time:200  s / page Erase time: Erase time: 2ms / block From [Nakamura02]

88. B.Supmonchai 2102-545 Digital ICs Memories 87 Semiconductor Memory Trends From [Itoh01] Quadruple every three year

89. B.Supmonchai 2102-545 Digital ICs Memories 88 Trends in Memory Cell Area From [Itoh01]

90. B.Supmonchai 2102-545 Digital ICs Memories 89 Technology feature size for different SRAM generations Technology Scaling Trends