1. SPD Control Board 16th February 2005

2. SPD Control Board (VFE control and SPD multiplicity) VFE’s control (I2C communication: SDA,SCL; clock; reset/trigger data) SPD multiplicity (count the number of SPD cells hit by a charged particle in one bunch crossing) Parts of the control board:

3. SPD Control Board (location) There are 8 crates (4+4) with 2 slots available for SPD CB. Every CB must be in charge of: –12 CB will be in charge of 7 VFE: 84.(crates 1,3 and 4) –4 CB will be in charge of 4 VFE: 16.(crate 2) –84+16=100 VFE. –(see next pictures)

4. Crates 4 45836791011121314 SPD control 2 15 : SPD control Boards 7 8 SPD Control Board (location)

5. SPD Control Board (VFE control and SPD multiplicity)

6. SPD Control Board (VFE control) SPECS Mezzanine CDC I2C LVDS I2C to 7 VFEs and 1 regulators board 8 clock channels available CDC: Clock Distribution Chip SPECS VFE’s control Control part contents: 1 SPECS mezzanine 2 Clock Distribution Chips (CDC) 24 DS92LV010 8 RJ45 connectors (7 for the VFE and 1 for regulators board) 8 AD8138 differential clock amplifier

7. SPD Control Board (VFE control) SPECS mezzanine: SCL_out, SDA_in, SDA_out Delay Chip, SPD multiplicity FPGA and optical mezzanine directly connected to SCL_out and SDA_out (pull-up) of the mezzanine board Mezzanine I2C bus LVDS conversion:

8. SPD Control Board (VFE control) RJ45 connectors (4 channels prototype) SPECS mezzanine connectors Delay Chip AD8138 DS92LV010

9. SPD Control Board (SPD multiplicity) Data from PS: Data deserialized using DS90CR216 Data processed by a FPGA controlled through and I2C link coming from SPECS mezzanine. Data sended using the optical mezzanine:single- channel (32 bits at 40Mhz) described in LHCB technical note: The optical transmitters for the LHCb Calorimeters prepared by the Bologna group. The trigger FPGA will supply clock and control signals to the optical mezzanine. I2C link connected to SPECS mezzanine. Power for the optical mezzanine also coming from the carrier board.

10. SPD Control Board (SPD multiplicity) Data from PS (7x3) FPGA Single-channel optical mezzanine DS90CR216 (7x21) 32 b Control and monitoring signals I2C from SPECS mezzanine Optical link

11. SPD Control Board (SPD multiplicity) FPGA schematic for the trigger part:

12. SPD Control Board (SPD multiplicity) Data synchronization for trigger validation:

13. SPD Control Board (SPD multiplicity) Channel synchronization:

14. SPD Control Board Control Board schematic for 4 channels (First prototype to communicate with 4 VFE). FPGA for SPD multiplicity part simulated. Board schematic for the SPD multiplicity part. Present status: