1. EE3230 積體電路設計導論 Introduction to Integrated Circuits Design Class Information Fall, 2014
Other handouts
In class quiz
Course schedule with due dates
To handout next time
HW#1
Project Description
Prof. Meng-Fan Chang (張孟凡)
Department of Electrical Engineering
National Tsing Hua University (NTHU), Taiwan

2. Course Contents “Introduction” to integrated circuits Course goals
CMOS devices, manufacturing technology, logic gates and building blocks.
Course goals
Ability to design and optimize CMOS circuits with different constraints: size (cost), speed and power dissipation
Learn various IC-design CAD tools
Circuit-simulation: HSPICE
IC-Layout: Laker
Verification (DRC, LVS) & RC-Extraction : Calibre
Course prerequisites
Electronics, Logic Designs, ( and Analog Circuit Designs)

3. Course Administration
Instructor: Prof. Marvin Meng-Fan Chang (張孟凡)
Office Hours: Thursdays 14:10– 14:40 AM or by appointment
Office: Delta Building (台達館861);
助教 (TA):
賴乙婷, 洪睿渝, 林建呈, 林鉦峻, 李岳陞, 林文章, 羅介甫
=>
TA office hours: TBD, at 台達館826
Course web:
Labs
Room: EECS Workstation Room
Evening Hours: Thursdays 18:30~20:30 (不點名)
Day-time Hours:
Oct. 30, Nov. 20, 13:10~14:00 (class-time)
computer accounts are automatic, if have never had an account in CSE I will have (or soon have) a listing of userids/passwords.
seating chart – assignment for Thursday – xerox copy of your photo ID
pick a seat for the semester and sit there (or nearby) for rest of semester
room size -

4. Course Administration - II
Text Book:
“Digital Integrated Circuits: A Design Perspective” by Rabaey
References:
“Neil H. E. Weste and David Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 3nd Ed., Addison Wesley, 2005”, by Ashok K. Sharma
IEEE papers
Slides:
pdf on the course web page after lectures

5. Grade Policy Midterm-1 exam.: 20% Midterm-2 exam. : 20%
Oct. 27, 2014
Midterm-2 exam. : 20%
Dec. 1, 2014
Final exam. (x1): 15%
Jan. 12, 2014
Project (x1): 20%
Homework (x5): 25%
2 students per team
Each student should present his/her HW separately
One student present the project for each team
Homework Out/In: Mondays (1:20pm)
Late HW policy: 0~1 week: 50%, >1weeks:0%

6. Class Schedule No lectures on Sept. 22, Sept. 25, Oct. 30 and Nov. 20
as Lab hours : Oct. 30 & Nov. 20
Make-up classes: (5x50=250min.)
Each class start from 13:10 (10min earlier)
15 weeks x 10 min x 2 = 300 min.
如有臨時停課 – make up classes on Tuesday evenings
computer accounts are automatic, if have never had an account in CSE I will have (or soon have) a listing of userids/passwords.
seating chart – assignment for Thursday – xerox copy of your photo ID
pick a seat for the semester and sit there (or nearby) for rest of semester
room size -

7. IC Design Courses in NTHU_EE - II
大三/大四
積體電路設計導論
積體電路設計實習 (IC Lab)
類比電路分析與設計 1 & 2
積體電路設計自動化概論
生醫積體電路設計導論
研究所
超大型積體電路設計
超大型機體電路數訊號處理
計算機算數
系統晶片實體設計
系統晶片設計實驗
超大型積體電路測試
半導體記憶體測試
類比電路設計
有線通訊積體電路設計
混合式無線通訊積體電路設計
射頻積體電路設計
通訊系統晶片設計
內嵌式記憶體電路設計
先進記憶體電路設計
Others
Memory
BIST & Test
SRAM
Flash RF
DRAM
Analog
Digital BB

8. 課程內容 Introductions CMOS Devices and IC Process
Static and Dynamic CMOS Gates (Combination Logics)
Interconnects and Parasitic Effects
Sequential CMOS Circuits
Memories and Emerging Technologies
IC Design Methodologies
Low-Power Design Methodology
Design Issues in Nano-scale IC
Design for Test
3D-IC