1. 1

2. CAD Challenges for Leading-Edge Multimedia Designs Ira Chayut, Verification Architect (opinions are my own and do not necessarily represent the opinion of my employer)

3. 3 Topics Unique Requirements Functional Verification Synthesis Physical Design Manufacturability Costs Conclusions

4. 4 Unique Requirements Short design cycles Large international teams Among the most complex and largest commercial creations

5. 5 Example: PS3 Graphics Chip More than 300M transistors About the same as the sum all of the following: XBOX GPU (60M) PS2 Graphics Synthesizer (43M) Game Cube Flipper (51M) Game Cube Gekko (21M) XBOX Pentium3 CPU (9M) PS2 Emotion Engine (10.5M) Athlon FX 55 (105.9M)

6. 6 Each Generation Demands More Copyright © NVIDIA Corporation 2005

7. 7 Looking Into the Crystal Ball Features are set by the software industry leaders – we have to guess when new features will be required by the market Shorter development cycles decrease the fuzziness in our predictions

8. 8 The Family Grows Quickly Time matters - each new flagship product must be followed by derivatives – almost concurrently

9. Design Flow Drivers Class Definitions C-models Validation Physical Verification Custom cells Test Insertion Logic Verification RTL Micro- architecture Floor Plan Test Reqmnts Speed/PWR/Area Requirements Data Path / STD Cell Place&Route; Timing Optimize; Data Path Foundry Reqmnts Foundry Data External Reqmnts Emulation Architecture & Algorithms Simulation TapeOut Architecture ASIC Physical Design Software Marketing Operations Sales 9

10. 10 Size Matters We are quickly approaching 1 Billion transistors with high logic-to-memory ratios The complexity of our designs is growing faster than the number of transistors All aspects of chip design affected, including: Verification, Synthesis, Physical Design, and Manufacturability

11. 11 Complexity Increases Exponentially Chip component count increases exponentially over time (Moore’s law) Interactions increase super-exponentially IP reuse and parallel design teams mean more functions per chip Verification gets combinatorially more difficult Transistors per chip 0 200 400 600 800 1000 1200 1400 1600 19952000200520102015 Year Millions of transistors

12. 12 Functional Verification Speed matters – Multimedia designs have a large pool of legacy tests, many of which are long running Multiple vendor CAD tools must inter-operate smoothly Verification now limits what features make it to silicon

13. 13 Why Verification is Unable to Keep Up Verification effort gets combinatorially more difficult as functions are added BUT Verification staffing/time cannot be made combinatorially larger to compensate AND Chip lifetimes are short, which decreases the time available for verification

14. 14 Emulation – Necessary and Costly $100 Million worth of emulators.... and growing Multiple boxes needed for a single chip

15. 15 Synthesis Synthesize early and synthesize often – CAD tools must support early synthesis to provide area, timing, and power estimates Must have better correlation between logic synthesis and post-layout results Early synthesis and layout can change the architecture and the design – this is only possible if problems are caught early in the design cycle ECO support is growing in importance

16. 16 Physical Design Deep submicron designs pose new problems for timing, power, and signal integrity Leading-edge multimedia designs are so large that we have to decompose the problem into partitions The number of partitions is growing and the size of chips (in clock cycles) is increasing Timing budgeting across partitions can be very wasteful – CAD tools must be able to work across partitions (at least “skin deep”) ECO support is growing in importance

17. 17 Holistic Approach CAD tools and flow must consider power, area, and timing throughout the design process Information from each tool must be able to fed back and forward to other tools in the flow Each chip must be able to choose the best vendor’s tool for each step

18. 18 Manufacturability Deep submicron technologies are much more affected by tiny variations between dies – CAD tools need to help increase yields by designing in margins (realizing that there are tradeoffs between these margins and size/speed) At-speed wafer testing of enormous chips require on-chip support – CAD tools must make this automatic and painless with minimal silicon cost

19. 19 Money Matters The costs of CAD tools and R&D staff are growing faster than the Multimedia TAM CAD tools must decrease their cost-per-seat CAD tools must make each engineer more productive over the entire design cycle

20. 20 Conclusions Size matters Performance matters Inter-operability matters Holistic view matters Money matters