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® SRAM Overview. ® Slide 2 Objectives n What is SRAM? l Memory vs. Storage l Terminology l Static vs. Dynamic l Random vs. Sequential 11110101 11010010.

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Presentation on theme: "® SRAM Overview. ® Slide 2 Objectives n What is SRAM? l Memory vs. Storage l Terminology l Static vs. Dynamic l Random vs. Sequential 11110101 11010010."— Presentation transcript:

1 ® SRAM Overview

2 ® Slide 2 Objectives n What is SRAM? l Memory vs. Storage l Terminology l Static vs. Dynamic l Random vs. Sequential 11110101 11010010 00010010 01111010 00011010 11010010 Address 0 Address n 12 3456 78 n SRAM Features l Asynchronous vs. Synchronous l Pipelined vs. Flow-Through l Burst Mode l Zero Bus Turnaround (ZBT)

3 ® Slide 3 Memory vs. Storage n Memory l Volatile l Fast Access n Storage l Non-volatile l Large Capacity l Slower Access

4 ® Slide 4 Terminology n Bits n Bytes n Density n Width n Depth n Speed 11110101 11010010 00010010 01111010 00011010 11010010 12345678 Address n. Address 0 Address 1..

5 ® Slide 5 Memory Read & Write 0001101000011010 READWRITE

6 ® Slide 6 Access Time Time Request Read / Write Data Read / Written Access Time (Speed)

7 ® Slide 7 Static vs. Dynamic Refresh

8 ® Slide 8 n Random Access Memory n Sequentia l Access Memory Random vs. Sequential DATA Control 01010110 00011010 11110101 11010010 01010010 01111010 DATA ADDRESS Control 01010110 00011010 11110101 11010010 01010010 01111010

9 ® Slide 9 Static Random Access Memory SRAM 4 M 512K X 8 ADDRESS DATA Control

10 ® Slide 10 Asynchronous vs. Synchronous Addr /Cntrl Data Clock CPUSRAM n Asynchronous SRAM l CPU controls all memory timing n Synchronous SRAM l Clock controls memory timing l CPU enables Addr /Cntrl Data Clock CPUSRAM

11 ® Slide 11 Pipelined vs. Flow-Through n Flow-Through n Pipelined Memory Cells Data Out Memory Cells Data Out Register Data

12 ® Slide 12 Burst Mode n Non-Burst Mode n Burst Mode Address aData (a) SRAM Non-Burst Mode Address a SRAM Burst Mode Data (a) Data (b) Data (c) Data (d)

13 ® Slide 13 Zero Bus Turnaround (ZBT) SRAM Data Bus WriteIdle ReadIdle Bus Turnaround from Write to Read ZBT SRAM Data Bus WriteReadWriteReadWrite No idle time between Reads and Writes

14 ® Slide 14 Summary n Terminology n Data storage types n SRAM features SRAM 4 M 512K X 8 ADDRESS DATA Control


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