1. Chapter 6: Internal Memory Computer Architecture Chapter 6 : Internal Memory Memory Processor Input/Output

2. Introduction Semiconductor memory subsystems including ROM, DRAM, SDRAM memories. Memory cell - Basic element of semiconductor memory. Has 3 function terminals (select,control,writing or reading)-carrying electrical signal. Error control techniques used to enhance the memory reliability Chapter 6 : Internal Memory

3. Semiconductor Memory Types Chapter 6 : Internal Memory

4. Semiconductor Memory Semiconductor memory properties :- –Exhibits 2 stable states to represent binary 1 and 0 –Capable of being written into (at least once), to set the state. –Capable of being read to sense the state. Chapter 6 : Internal Memory

5. Memory Cell Operation Select –read or write operation Control – indicates the read or write operation Chapter 6 : Internal Memory

6. RAM Read data from memory and write new data into the memory easily and rapidly. Accomplished through the use of electrical signals. Volatile – needs constant power supply to avoid data lost. Temporary storage. Two traditional RAM –Dynamic RAM (DRAM) –Static RAM (SRAM). Note : Dynamic or static refers to the RAM technology. Chapter 6 : Internal Memory

7. Dynamic RAM (DRAM) Cells that store data as charge in capacitors Presence or absence of charge represent 1 or 0. Charges leak/discharge-Need periodic charge refreshing to maintain data storage. Dynamic-tendency of the stored charge to leak away, even with power continuously applied. Simpler construction Smaller per bit Less expensive Need refresh circuits Slower Main memory Essentially analogue device –Level of charge determines value of 1 or 0 Chapter 6 : Internal Memory

8. Dynamic RAM Structure Chapter 6 : Internal Memory

9. DRAM Operation Address line active when bit read or written –Transistor switch closed (current flows) Write –Voltage to bit line High for 1 low for 0 –Then signal address line Transfers charge to capacitor Read –Address line selected transistor turns on –Charge from capacitor fed via bit line to sense amplifier Compares with reference value to determine 0 or 1 –Capacitor charge must be restored Chapter 6 : Internal Memory

10. Static RAM (SRAM) Digital device -using same logic elements as used in processor Bits stored as on/off switches No charges to leak No refreshing needed when powered – no need refresh circuits to retain data. More complex construction As in the DRAM, address line used to open/close a switch. Larger per bit More expensive Faster than DRAM Cache –Uses flip-flops Chapter 6 : Internal Memory

11. Static RAM Structure Chapter 6 : Internal Memory

12. Static RAM Operation Transistor arrangement gives stable logic state State 1 –C 1 high, C 2 low –T 1 T 4 off, T 2 T 3 on State 0 –C 2 high, C 1 low –T 2 T 3 off, T 1 T 4 on Address line transistors T 5 T 6 is switch Write – apply value to B & compliment to B Read – value is on line B Chapter 6 : Internal Memory

13. SRAM vs DRAM Both volatile –Power needed to preserve data Temporary storage Dynamic cell –Simpler to build, smaller –More dense –Less expensive –Needs refresh –Larger memory units Static cell –Faster –Cache Chapter 6: Internal Memory

14. Read Only Memory (ROM) Permanent storage –Nonvolatile Applications of ROM –Microprogramming –Library subroutines –System programs (BIOS: Basic Input Output System) –Function tables Chapter 6 : Internal Memory

15. ROM at Work While RAM uses transistors to turn on or off access to a capacitor at each intersection, ROM uses a diode to connect the lines if the value is 1. If the value is 0, then the lines are not connected at all. Figure. BIOS uses Flash memory, a type of ROM. Chapter 6 : Internal Memory

16. Types of ROM Written during manufacture-mask programed –Very expensive for small runs Programmable (once) –PROM –Needs special equipment to program Read “mostly” – another variation on ROM –Erasable Programmable (EPROM) Erased by UV (ultraviolet radiation) Like PROM it is read and written electrically –Electrically Erasable (EEPROM) Takes much longer to write than read Only addressed byte(s) are updated –Flash memory Erase whole memory electrically, cells are erased in a “flash” or single action,1/2 cost and functionality of EPROM and EEPROM, Erase blocks Not erase at the byte level, use single transistor per bit. Chapter 6 : Internal Memory

17. 17 Organisation in detail A 16Mbit chip can be organised as 1M of 16 bit words A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array –Reduces number of address pins Multiplex row address and column address 11 pins to address (2 11 =2048) Adding one more pin doubles range of values so x4 capacity Chapter 6 : Internal Memory

18. Typical 16 Mb DRAM (4M x 4) Chapter 6 : Internal Memory

19. Typical 16 Mb DRAM (4M x 4) – details 4 bits are read and written at a time. Memory array is organized as 4 square arrays of 2048 x 2048 elements. Elements are connected by both horizontal (rows) and vertical (columns) line. Each horizontal line connects to the Select terminal of each cell in its row. Each vertical line connects to data in/sense terminal of each cell in its column.

20. Typical 16 Mb DRAM (4M x 4) – details Address lines supply the address of the word to be selected. 11 lines are needed to select one of 2048 rows. These lines are fed into a row decoder, which has 11 lines of input and 2048 lines for output. Similarly, additional 11 address lines select one of 2048 columns of 4 bits per column. Four data lines are used for the input and output of 4 bits to and from a data buffer.

21. Typical 16 Mb DRAM (4M x 4) – details Data input buffer (4 bits) – data to be written Data output buffer (4 bits) – data to be sensed/read. Only 4 bits read/write  must be multiple DRAM connected to the memory controller to read/write a word of data to the bus. Only 11 address lines (A0-A10) used instead of 22 required address lines. –First 11 address signals –row address. –Other 11 address signals – column address.

22. Typical 16 Mb DRAM (4M x 4) – details Timing and control signals –RAS – row address select –CAS – column address select –WE – Write Enable (Write operation) –OE - Output Enable (Read Operation) All DRAMs require refresh operation Refresh circuit included on chip Disable chip – while the data cells refreshed Count through rows Read & Write back into the same location. Takes time Slows down apparent performance

23. Chip Packaging For 1M words, a total of 20 address pins (2 20 =1M) i.e A0-A19 D0-D7 ; 8 lines for data read out Vcc power supply Vss ground pin CE (Chip enable) pin, if > 1 chip, CE indicates which chip is meant to pick up the address in the bus. Vpp program voltage supplied-write operation. Chapter 6 : Internal Memory 8 Mbit EPROM

24. Chip Packaging (2) For 1M words, a total of 20pins (2 20 =1M) D0-D7 8 lines for data read out Vcc power supply Vss ground pin CE Chip enable pin, if > 1 chip, CE indicates which chip is meant to pick up the address in the bus. Vpp program voltage supplied Chapter 6 : Internal Memory

25. Chip Packaging (3) DRAM Data pins are input/output – RAM can be updated WE and OE indicates write or read operation DRAM is accessed by Row and Column and the address is multiplexed, so for 4M row/column combinations only 11 pins are needed (2 11 x 2 11 = 2 22 =4M) NC (no connect). Chapter 6 : Internal Memory 16 Mbit DRAM 4M X 4

26. 256kByte Module Organisation Chapter 6 : Internal Memory

27. 1MByte Module Organisation Chapter 6 : Internal Memory

28. Chip Packaging (3) DRAM, ROM Pins are input/output  updating WE and OE  write or read operation DRAM is accessed by Row and Column and the address is multiplexed, so for 4M row/column combinations only 11 pins are needed (2 11 x 2 11 = 2 22 =4M) NC (no connect) is provided to set the pins number to an even state. Chapter 6 : Internal Memory

29. 256kByte Module Organisation Chapter 6 : Internal Memory

30. 1MByte Module Organisation Chapter 6 : Internal Memory

31. Error Correction Hard Failure –Permanent physical defect-cells cannot reliably store data. Soft Error –Random, non-destructive-alters the contents of cells. –No permanent damage to memory Detected using Hamming error correcting code Chapter 6 : Internal Memory

32. Error Correcting Code Function Chapter 6 : Internal Memory Both data (M bits) and code generated by f (K bits) are stored. During fetch, new K code bits generated from the M data bits by f and compared with fetched code bits Comparison yields 3 results a) No errors b) corrected errors c) errors detected but not possible to correct it.

33. Hamming Error Correcting Codes (2) (a) Encoding of 1100 (b) Even parity added (c) Error in AC Chapter 6 : Internal Memory

34. Advanced DRAM Organization Basic DRAM same since first RAM chips –Constrained – internal architecture and interface to the processor’s memory bus. -Asynchronous – needs wait state during memory read and write cycle. -Access time of DRAM is more compared to CPU’s clock. -CPU forced to enter wait state for one or more clocks as required. Enhanced DRAM –Contains small SRAM (cache) between processor & DRAM main memory. –SRAM holds last line read Chapter 6 : Internal Memory

35. Synchronous DRAM (SDRAM) Access is synchronized with an external clock, unlike traditional DRAM (asynchronous) Since SDRAM moves data in time with system clock, CPU knows when data will be ready CPU does not have to wait, it can do something else. Burst mode (eliminates address set up time, column and row line pre-charge time) allows SDRAM to set up stream of data and fire it out in block Enhanced version of SDRAM-Double Data Rate: DDR-SDRAM. Chapter 6 : Internal Memory

36. DDR SDRAM SDRAM can only send data once per clock Double-data-rate SDRAM can send data twice per clock cycle –Rising edge and falling edge Chapter Four : Internal Memory

37. SDRAM (Synchronous DRAM) Chapter Four : Internal Memory

38. SDRAM Read Timing Chapter Four : Internal Memory

39. RAMBUS Adopted by Intel for Pentium & Itanium Main competitor to SDRAM Vertical package – all pins on one side Data exchange over 28 wires <= 12cm long Bus addresses up to 320 RDRAM chips at 1.6Gbps, not controlled by CAS RAS W/R or CE Asynchronous block protocol –480ns access time –Then 1.6 Gbps Chapter Four : Internal Memory

40. RAMBUS Diagram Chapter Four : Internal Memory

41. Cache DRAM (CDRAM) Integrates small SRAM cache (16 kb) onto generic DRAM chip DRAM chip with an on-chip cache memory. Used as true cache –64-bit lines –Effective for ordinary random access To support serial access of block of data –E.g. refresh bit-mapped screen CDRAM can pre-fetch data from DRAM into SRAM buffer Subsequent accesses solely to SRAM Chapter Four : Internal Memory