1. COMPUTER ORGANIZATIONS CSNB123

2. COMPUTER ORGANIZATIONS CSNB123 Expected Course Outcome #Course OutcomeCoverage 1Explain the concepts that underlie modern computer architecture, its evolution, functions and organization.  2Identify the best organization of a computer for achieving the best performance when asked to make a selection from the current market. 3Demonstrate the flow of an instruction cycle.  4Differentiate types of memory components in terms of its technology and usage. 5Convert integer and floating point numbers to its internal data representation. 6Construct a series of computer instructions to perform low-level processor operations.  7Explain the RISC and CISC computers, and single core and multi-core computers May2014Systems and Networking2

3. COMPUTER ORGANIZATIONS CSNB123 What is a program? May 2014Systems and Networking3 arithmetic or logical operation is done a different set of control signals is needed

4. COMPUTER ORGANIZATIONS CSNB123 Function of Control Unit A unique code for each operation  Example: ADD, MOVE May 2014Systems and Networking4 Hardware Segment Issues control signals Accept codes

5. COMPUTER ORGANIZATIONS CSNB123 Computer Components May 2014Systems and Networking5 PC = Program Counter IR = Instruction Register MAR = Memory Address Register MBR = Memory Buffer Register I/O AR = Input/Output Address Register I/O BR = Input/Output Buffer Register Computer Central Processing Unit (CPU) I/O Module Buffers Main Memory Instruction...... Data... 012...012... PC MAR MBR I/O AR I/O BR IR Execution Unit.. System Bus

6. COMPUTER ORGANIZATIONS CSNB123 Instruction Cycle Two steps  Fetch cycle  Execute cycle May 2014Systems and Networking6 Start Fetch Next Instruction Execute Instruction Halt Fetch cycle Execution cycle

7. COMPUTER ORGANIZATIONS CSNB123 Fetch Cycle Program Counter (PC) Holds address of next instruction to fetch Processor Fetch instruction from memory location pointed to by PC Increment PC Instruction Register (IR) Load the instruction Processor Interprets instruction Perform required actions May 2014Systems and Networking7

8. COMPUTER ORGANIZATIONS CSNB123 Execute Cycle May 2014Systems and Networking8 Processor - Memory Execution Cycle Processor I/O Data Processing Control

9. COMPUTER ORGANIZATIONS CSNB123 Program Execution - Example May 2014Systems and Networking9

10. COMPUTER ORGANIZATIONS CSNB123 Instruction Cycle State Diagram May 2014Systems and Networking10 Instruction Fetch Instruction Address Calculation Instruction Operation Decoding Operand Address Calculation Data Operation Operand Address Calculation Operand Fetch Operand Store Multiple Operands Multiple Results Return for string or vector data Instruction complete, Fetch next instruction

11. COMPUTER ORGANIZATIONS CSNB123 Interrupts Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing May 2014Systems and Networking11

12. COMPUTER ORGANIZATIONS CSNB123 Classes of Interrupts Program  Stack overflow, division by zero Timer  Generated by internal processor timer  Used in pre-emptive multi-tasking I/O  I/O controller – signal the error condition Hardware failure  Power failure May 2014Systems and Networking12

13. COMPUTER ORGANIZATIONS CSNB123 Interrupt – Program Flow Control May 2014Systems and Networking13

14. COMPUTER ORGANIZATIONS CSNB123 Interrupt Cycle Added to instruction cycle May 2014Systems and Networking14 Start Fetch Next Instruction Execute Instruction Halt Fetch cycle Execution cycle Check for interrupt; process interrupt Interrupt cycle Interrupts disabled Interrupts enabled

15. COMPUTER ORGANIZATIONS CSNB123 Interrupt Cycle (Cont.) Processor checks for interrupt  Indicated by an interrupt signal If no interrupt, fetch next instruction If interrupt pending:  Suspend execution of current program  Save context  Set PC to start address of interrupt handler routine  Process interrupt  Restore context and continue interrupted program May 2014Systems and Networking15

16. COMPUTER ORGANIZATIONS CSNB123 Transfer of Control via Interrupts May 2014Systems and Networking16

17. COMPUTER ORGANIZATIONS CSNB123 Program Timing: Short I/O Wait May 2014Systems and Networking17

18. COMPUTER ORGANIZATIONS CSNB123 Program Timing: Long I/O Wait May 2014Systems and Networking18

19. COMPUTER ORGANIZATIONS CSNB123 Multiple Interrupts - Approaches Disable interrupts  Processor - ignore that interrupt request signal Situation: executing the program and interrupt occurs – interrupts are disable immediately  Pending - checked after the processor has enabled interrupts After interrupt handler routine completes  Enable interrupts before resume  Check additional interrupt  Handle interrupt in strict sequential order May 2014Systems and Networking19

20. COMPUTER ORGANIZATIONS CSNB123 Multiple Interrupts – Sequential Interrupt Processing May 2014Systems and Networking20

21. COMPUTER ORGANIZATIONS CSNB123 Multiple Interrupts – Nested Interrupt Processing May 2014Systems and Networking21

22. COMPUTER ORGANIZATIONS CSNB123 Multiple Interrupts – Approaches (Cont.) Define priorities  Low priority interrupts can be interrupted by higher priority interrupts  When higher priority interrupt has been processed, processor returns to previous interrupt May 2014Systems and Networking22

23. COMPUTER ORGANIZATIONS CSNB123 Time Sequence of Multiple Interrupts - Example May 2014Systems and Networking23

24. COMPUTER ORGANIZATIONS CSNB123 Time Sequence of Multiple Interrupts – Example (Cont) May 2014Systems and Networking24 SteptDescription 10 Program begins 210 Printer interrupt occurs Place user information on the system stack Execution continues at the printer interrupt service routine (ISR) 315 Routine in (2) still executing Communication interrupt occurs  higher priority than printer 420 Routine in (3) still executing Disk interrupt occurs  low priority than communication ISR but priority is higher than printer 525 Communication ISR is completed Continue to execute disk ISR 635 Disk ISR is completed Continue to execute printer ISR 740 Routine completes Return to the user program

25. COMPUTER ORGANIZATIONS CSNB123 Interconnection Structures Collection of paths connecting the various modules Modules:  Memory  Processor  I/O module May 2014Systems and Networking25

26. COMPUTER ORGANIZATIONS CSNB123 Modules: Major Form of Input and Output - Memory Word of data - Read from or written into the memory  Assigned a unique numerical address Nature of the operation – indicated by read and write control signals Address – specify the location for the operation May 2014Systems and Networking26

27. COMPUTER ORGANIZATIONS CSNB123 Modules: Major Form of Input and Output - Processor Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts May 2014Systems and Networking27

28. COMPUTER ORGANIZATIONS CSNB123 Modules: Major Form of Input and Output – I/O Module Operations;  Read  Write Control more than one external device External data path – input and output of data Send interrupt signals to CPU May 2014Systems and Networking28

29. COMPUTER ORGANIZATIONS CSNB123 Modules: Major Form of Input and Output May 2014Systems and Networking29

30. COMPUTER ORGANIZATIONS CSNB123 Types of Transfers Memory to processor: Processor reads instruction/data from memory Processor to memory: Processor writes data to memory I/O to processor: Processor reads data from I/O device (via I/O module) Processor to I/O: Processor sends data to I/O device I/O to/from memory: allowed to exchange data using Direct Memory Access (DMA) – exclude processor May 2014Systems and Networking30

31. COMPUTER ORGANIZATIONS CSNB123 Bus Interconnection Communication pathway connecting two or more devices Key characteristic: shared transmission medium Consists of multiple communication pathways/lines  Lines – transmit signals representing binary 1 and 0 – one data at a time May 2014Systems and Networking31

32. COMPUTER ORGANIZATIONS CSNB123 System Bus A bus that connects major computer components (CPU, memory, I/O) Computer interconnection structures – use one or more system buses Consists of 50 to hundreds of separate lines  Each line – function. E.g: power May 2014Systems and Networking32

33. COMPUTER ORGANIZATIONS CSNB123 Data Line Provide a path for moving data among system modules Collective – data bus May 2014Systems and Networking33

34. COMPUTER ORGANIZATIONS CSNB123 Data Bus Collective of data lines Width of the data bus - Number of lines;  32, 64, 128 …  Key factor in determining overall system performance Number of data lines – represents number of data can be transferred at a time May 2014Systems and Networking34

35. COMPUTER ORGANIZATIONS CSNB123 Address Lines Designate the source or destination of the data on data bus May 2014Systems and Networking35

36. COMPUTER ORGANIZATIONS CSNB123 Address Bus Collective of address lines Width of the address bus determines the maximum possible memory capacity of the system May 2014Systems and Networking36

37. COMPUTER ORGANIZATIONS CSNB123 Control Lines Used to control the access to and the use of the data and address lines Control signals transmit both command and timing information among system modules  Command signals – specify operations to be performed  Timing signals – validity of data and address information May 2014Systems and Networking37

38. COMPUTER ORGANIZATIONS CSNB123 Bus Interconnection Scheme May 2014Systems and Networking38

39. COMPUTER ORGANIZATIONS CSNB123 Operation of the Bus May 2014Systems and Networking39 Send data  Obtain the use of the bus  Transfer data via the bus Request data  Obtain the use of the bus  Transfer a request to the other module over appropriate control and address lines

40. COMPUTER ORGANIZATIONS CSNB123 System Bus - Physical Number of parallel electrical conductors – metal lines on the circuit board May 2014Systems and Networking40

41. COMPUTER ORGANIZATIONS CSNB123 Physical Realization of Bus Architecture May 2014Systems and Networking41

42. COMPUTER ORGANIZATIONS CSNB123 Single Bus - Problem Many of devices on one bus leads to:  Propagation delays Long data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity Most systems use multiple buses to overcome these problems May 2014Systems and Networking42

43. COMPUTER ORGANIZATIONS CSNB123 Traditional (ISA) - with cache May 2014Systems and Networking43

44. COMPUTER ORGANIZATIONS CSNB123 High Performance Bus May 2014Systems and Networking44

45. COMPUTER ORGANIZATIONS CSNB123 Types of Bus Dedicated  Separate data & address lines Multiplexed  Shared lines  Address valid or data valid control line  Advantage Fewer lines  Disadvantages More complex control Reduction in performance May 2014Systems and Networking45

46. COMPUTER ORGANIZATIONS CSNB123 Bus Arbitration Process of insuring only 1 devices places information onto the bus at a time Master - slave mechanism Master is given control of the bus and can place information onto it Slave receives the information from the master  Two methods Centralized Decentralized May 2014Systems and Networking46

47. COMPUTER ORGANIZATIONS CSNB123 Master–Slave Mechanism: Methods Centralized  Central bus controller mediates all device requests for the bus  May be part of CPU or a hardware of its own (arbiter) Decentralized  No centralized controller  All devices contain logic to control access to the bus May 2014Systems and Networking47

48. COMPUTER ORGANIZATIONS CSNB123 Bus Timing Synchronous  Occurrence of events on the bus is determined by the clock  All events start at the beginning of a clock cycle  Example: PCI bus (Peripheral Component Interface bus Asynchronous  The occurrence of one event follows and depends on the occurrence of a previous event  More flexible than synchronous bus but more complicated as well  Accommodates wider range of device speeds  Example: Futurebus+ May 2014Systems and Networking48

49. COMPUTER ORGANIZATIONS CSNB123 Synchronous Timing Diagram May 2014Systems and Networking49

50. COMPUTER ORGANIZATIONS CSNB123 Asynchronous Timing – Read Diagram May 2014Systems and Networking50

51. COMPUTER ORGANIZATIONS CSNB123 Asynchronous Timing – Write Diagram May 2014Systems and Networking51

52. COMPUTER ORGANIZATIONS CSNB123 Additional Reference William Stallings, Computer Organization and Architecture: Designing for Performance, 8th. Edition, Prentice-Hall Inc., 2010 May2014Systems and Networking52

53. COMPUTER ORGANIZATIONS CSNB123 May2014Systems and Networking53 This teaching material is belongs to Systems and Networking Department College of Information Technology Universiti Tenaga Nasional (UNITEN) Malaysia 2014