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8. 8 Class of Service Distribution SW/HW interface Clusters of VPUs Clusters of VPUs Clusters of VPUs LBS Arbitration Clusters of VPUs Clusters of VPUs Clusters of VPUs LBS Arbitration Clusters of VPUs Clusters of VPUs Clusters of VPUs LBS Arbitration

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11. S/W emulator or H/W DSP system Input vectors Output reports LBS1 Classifier Stratix II 180 PROCStar II 11 PCI Bus DDR2 LBS2 DDR2 LBS3LBS4 Main Bus : Data In and Controls Stratix II 180 Ring Bus Per LBS registers

12. Load Balancing Switch (LBS) DDR2 Controls Bank A LBS 1-4 Stratix II 180 FPGA DDR2 Controls Bank B I/O – LBS Control Block Data flow NIOS cluster 12 Bus Control Block

13. 13 Header Data 1 to N of 32-bit Words Tail …… Unused Nios Number Data Length NVector ID/Command Type 8-bit32-bit16-bit Version 4-bit SW/HW Control 1-bit Type 1-bit (Data/Command)

14. Main Controller unit Stratix II FPGA Output Writer Cluster Arbiter NIOS II System Input Reader Cluster Arbiter NIOS II System Control FIFO Input Port FIFO Output Port Control Cluster Arbiter NIOS II System Muxed output data bus Input data bus Control and Status Statistics Reporter 14 Busses Control Block

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17. 17 Module ModuleLogicutilization% Memory (M4K) % Peripheral IPs (MegaFIFO, PLLs, etc.) 3,1002162 User System (All VPUs + LBS)42,0003067588 Single VPU6,7754.711215 LBS Logic1,350130.5 Total usage of chip resources 45,8963269190 Total available 143,000100768100 VPU resource usage is based on basic VPUs and may be decreased by advanced configurations and policies.

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19. 19System Time of Service[sec]Throughput[Mbit/s]Impr SW (on Core2Duo E6600) 0.13.2 6 VPUs0.0020912238 2 Classes of 6 VPUs0.0013419160 3 Classes of 6 VPUs0.0008629793 4 Classes of 6 VPUs0.00064400125 VPU performance is based on basic VPUs and RR arbitration and may be increased for giving workload after perf. analysis by defining advanced configurations and policies.

20. 20System Time of Service[sec]Throughput[Mbit/s]Impr SW (on Core2Duo E6600) 2.92.3 6 VPUs0.2823.410 2 Classes of 6 VPUs0.1543.518.5 3 Classes of 6 VPUs0.016628.7 4 Classes of 6 VPUs0.0748838 VPU performance is based on basic VPUs and RR arbitration and may be increased for giving workload after perf. analysis by defining advanced configurations and policies.

21. 21System Time of Service[sec]Throughput[Mbit/s]Impr SW (on Core2Duo E6600) 1.12.9 One VPU1.2242.620.89 6 VPUs0.20815.435.3 2 Classes of 6 VPUs0.1129.110 3 Classes of 6 VPUs0.07443.6914.8 4 Classes of 6 VPUs0.06152.4618 VPU performance is based on basic VPUs and RR arbitration and may be increased for giving workload after perf. analysis by defining advanced configurations and policies.

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