2. Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

3. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Stored Program Architecture  Instruction Cycle ●Fetch an instruction from memory ●Decode the instruction ●Get the operands ●Execute the instruction  Where is the next instruction? Program Counter (PC) Instruction Pointer (IP)  Where is the operand? 9:28 AM Instructions (Program) Operands (Data) Opcode Operands Binary Operand 1 / 54

4. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. CPU  Datapath  Control Unit 9:28 AM Register File CU ALU 2 / 54

5. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. General-Purpose Register Organization 9:28 AM R1 R2 R3 R4 R5 R6 R7 MUX ALU 3 x 8 Decoder D SEL A SEL B SEL OPR Memory & I/O AB 3 / 54

6. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. General-Purpose Register Organization 9:28 AM R1 R2 R3 R4 R5 R6 R7 MUX ALU 3 x 8 Decoder D SEL A SEL B SEL OPR Memory & I/O AB Examples: OperationOPRA SEL B SEL D SEL R1 ← R2 − R3 R4 ← SHL R4 4 / 54

7. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. General-Purpose Register Organization 9:28 AM Examples: OperationOPRA SEL B SEL D SEL R1 ← R2 − R300101010011001 R4 ← SHL R411000100000100 Instructions (Program) Operands (Data) 00101 010 011 001 00 0000 0000 5 / 54

8. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Memory Interface  Address / Data Buses  Read / Write Control  Bidirectional / Unidirectional Data Bus 9:28 AM Read Write 6 / 54

9. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Building a Datapath  Datapath Elements 9:28 AM PC InstructionMemory Addr Data ALU Reg A (Read) Reg B (Read) Reg C (Write) Data A Data B Register File Data C Write a program & compile it. Where do you want to put it? Where is the first instruction? What comes out of memory? Where to perform operation? Where are the operands? Who well tell us which reg? Where to store result? Can we save this reg to mem? 32 7 / 54

10. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Building a Datapath  Datapath Elements 9:28 AM PC InstructionMemory Addr Data ALU DataMemory Addr Data Reg A (Read) Reg B (Read) Reg C (Write) Data A Data B Register File Data C 8 / 54

11. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Building a Datapath 9:28 AM PC InstructionMemory Addr Data ALU DataMemory Addr Data How can we read it back? Reg A (Read) Reg B (Read) Reg C (Write) Data A Data B Register File Data C 9 / 54

12. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Building a Datapath 9:28 AM PC InstructionMemory Addr Data ALU DataMemory Addr Data Finished executing instruction. Where is the next instruction? Why +4? MUX 4 Adder Reg A (Read) Reg B (Read) Reg C (Write) Data A Data B Register File Data C 10 / 54

13. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Building a Datapath 9:28 AM PC InstructionMemory Addr Data ALU DataMemory Addr Data MUX 4 Adder How can we add “immediate”? What if it is 8-bit negative? SignExtend Reg A (Read) Reg B (Read) Reg C (Write) Data A Data B Register File Data C 11 / 54

14. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Building a Datapath 9:28 AM PC InstructionMemory Addr Data ALU DataMemory Addr Data MUX 4 Adder SignExtend MUX What about “JMP Rel Disp”? It can be positive or negative! Reg A (Read) Reg B (Read) Reg C (Write) Data A Data B Register File Data C 12 / 54

15. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Building a Datapath 9:28 AM PC 4 DataMemory Addr Data SignExtend MUX Addr Data MUX InstructionMemory Shift Left 2 Adder Adder ALU Reg A (Read) Reg B (Read) Reg C (Write) Data A Data B Register File Data C 13 / 54

16. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Building a Datapath 9:28 AM PC 4 DataMemory Addr Data SignExtend A Data B MUX Addr Data MUX InstructionMemory Register File Shift Left 2 MUX Adder Adder ALU Data C Why the shift? Answer: Reg A (Read) Reg B (Read) Reg C (Write) 14 / 54

17. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Building a Datapath 9:28 AM PC 4 DataMemory Addr Data SignExtend A Data B MUX Addr Data MUX InstructionMemory Register File Shift Left 2 MUX Adder Adder ALU Data C Why not use ALU instead of another adder? Answer: Reg A (Read) Reg B (Read) Reg C (Write) 15 / 54

18. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Cy, Z, etc Adding Control Signals to the Datapath 9:28 AM PC 4 DataMemory Addr Data SignExtend A Data B 0 00MUXMUX1100MUXMUX111 Addr Data 1 11MUXMUX0011MUXMUX000 InstructionMemory Register File Shift Left 2 0 00MUXMUX1100MUXMUX111 Adder Adder ALU Data C Control Unit Opcode etc Reg A (Read) Reg B (Read) Reg C (Write) 16 / 54

19. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Adding Control Signals to the Datapath 9:28 AM PC 4 DataMemory Addr Data SignExtend A Data B 0 00MUXMUX1100MUXMUX111 Addr Data 1 11MUXMUX0011MUXMUX000 InstructionMemory Register File Shift Left 2 0 00MUXMUX1100MUXMUX111 Adder Adder ALU Data C Control Unit Reg A (Read) Reg B (Read) Reg C (Write) 17 / 54

20. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. A Simple Implementation Scheme  ALU Control 9:28 AM ALU 32 4 ALU Cntrl Cy Z slt R1, R2, R3 Cy = 1  Carry from last adder Z = 1  The result = 0 18 / 54

21. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. A Simple Implementation Scheme  Instruction Format ●Arithmetic/Logic 9:28 AM OpcodeOperand(s), Address, Code 0 6 RsRs 55556 RtRt RdRd ShiftFunct R d = R s Funct R t FunctALU OperationALU Cntrl Lines 100000Add0010 100010Subtract0110 100100AND0000 100101OR0001 101010SLT0111 Example: 00000000011001110010100000100000 Reg A (Read) Reg B (Read) Reg C (Write) Data A Data B Register File Data C 19 / 54

22. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. A Simple Implementation Scheme  Instruction Format ●Load Immediate 9:28 AM OpcodeOperand(s), Address, Code Lower R t = Value Upper R t = Value Example: R 1 = 12 00110100000000010000 0000 0000 1100 13 6 0 5516 RtRt Immediate (Lower) 160RtRt Immediate (Upper) 01000000000000010000 0000 20 / 54

23. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. A Simple Implementation Scheme  Instruction Format ●Load Memory 9:28 AM OpcodeOperand(s), Address, Code 35 6 RsRs 5516 RtRt Address R t = M [R s + Addr] 32 bits16 bits (can be positive or negative) Example: R 6 = M [R 4 – 1 ] 10001100100001101111 1111 21 / 54

24. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. A Simple Implementation Scheme  Instruction Format ●Store Memory 9:28 AM OpcodeOperand(s), Address, Code 43 6 RsRs 5516 RtRt Address M [R s + Addr] = R t Example: M [R 7 – 2 ] = R 9 10101100111010011111 1111 1111 1110 22 / 54

25. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. A Simple Implementation Scheme  Instruction Format ●JE Operation 9:28 AM OpcodeOperand(s), Address, Code 4 6 RsRs 5516 RtRt Offset If R s = R t then PC = PC + 4*Addr Example: 00010000001001001111 1111 PC is already incremented 23 / 54

26. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. MUXMUXMUXMUX Final Datapath Design 9:28 AM PC 4 DataMemory Addr Data SignExtend A Data B 0 00MUXMUX1100MUXMUX111 Addr Data 1 11MUXMUX0011MUXMUX000 InstructionMemory Register File Shift Left 2 0 00MUXMUX1100MUXMUX111 Adder Adder Data C Reg A (Read) Reg B (Read) Reg C (Write) ALU RsRs RtRt Offset, Addr, Immediate RtRt RdRd 24 / 54

27. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Program Setup  Write a Program  Assemble it  Store it in Memory 9:28 AM Example: 00110100000000010000 0000 0000 101000000000001 00000100000 3 4 0 1 0 0 0 A 0 0 2 1 0 8 2 0 048048 00010000001 1111 1111 1 0 2 1 F F F F 25 / 54

28. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands  Execute it 9:28 AM CLK PC I-Mem 0 ƮMƮM 3401000A (LLI R 1, 10) 130110 RsRs RtRt Immediate Reg A Sel 00 Data A Ʈ Reg 1 Reg C Sel Reg C Write ALU MUX 2 (Add) ALU Ctrl Mem MUX 10 Sign Ext 10 ALU Ʈ ALU 10 Data C Adder MUX 4 PC Adder Ʈ Adder Ʈ Reg 26 / 54

29. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Datapath Operation  How Fast Can the Clock Be? 9:28 AM CLK PC I-Mem 0 ƮMƮM 3401000A (LLI R 1, 10) Reg A Sel 00 Data A Ʈ Reg 1 Reg C Sel Reg C Write ALU MUX 2 (Add) ALU Ctrl Mem MUX 10 Sign Ext 10 ALU Ʈ ALU 10 Data C Adder MUX 4 PC Adder Ʈ clk Ʈ Reg 27 / 54

30. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands  Execute it 9:28 AM CLK PC I-Mem 4 00210820(Add R 1,R 1,R 1 ) Reg A Sel 110 Data A 1 Reg C Sel Reg C Write ALU MUX 2 (Add) ALU Ctrl Mem MUX 10 Data B 20 ALU 20 Data C Adder MUX 8 PC Adder 01132 RsRs RtRt FunctRdRd 10 Shift 0 4 0 1 2 0 10 28 / 54

31. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands  Execute it 9:28 AM CLK PC I-Mem 8 1021FFFF (JE R 1,R 1,-1) Reg A Sel 120 Data A 1 Reg C Sel Reg C Write ALU MUX 6 (Sub) ALU Ctrl 20 Data B 0 ALU 12 PC Adder 411– 1 RsRs RtRt Offset 4 8 1 1 2 10 20 10 PC Adder 2 8 Adder MUX 29 / 54

32. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Datapath Operation  How Fast Can the Clock Be? 9:28 AM CLK PC I-Mem 8 1021FFFF (JE R 1,R 1,-1) Reg A Sel 120 Data A 1 Reg C Sel Reg C Write ALU MUX 6 (Sub) ALU Ctrl 20 Data B 0 ALU 12 PC Adder 4 8 1 1 2 10 20 10 PC Adder 2 8 Adder MUX ƮMƮM Ʈ Reg Ʈ ALU 30 / 54

33. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Datapath Operation  How Fast Can the Clock Be? 9:28 AM CLK PC I-Mem 8 1021FFFF (JE R 1,R 1,-1) Reg A Sel 120 Data A 1 Reg C Sel Reg C Write ALU MUX 6 (Sub) ALU Ctrl 20 Data B 0 ALU 12 PC Adder 4 8 1 1 2 10 20 10 PC Adder 2 8 Adder MUX Ʈ Adder Ʈ clk Ʈ Reg Ʈ ALU ƮMƮM 31 / 54

34. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Single-Cycle Implementation  Fetch Instruction  Decode Instruction  Get Operands  Execute it 9:28 AM CLK PC I-Mem i 8C640007 (LD R 4,[R 3 +7]) 35347 RsRs RtRt Address Reg A Sel 3 d Data A 4 Reg C Sel Reg C Write ALU MUX 2 (Add) ALU Ctrl Mem MUX 7 Sign Ext d +7 ALU v Data C D-Mem v 32 / 54

35. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Single-Cycle Implementation  Clock Speed? 9:28 AM CLK PC I-Mem i 8C640007 (LD R 4,[R 3 +7]) Reg A Sel 3 d Data A 4 Reg C Sel Reg C Write ALU MUX 2 (Add) ALU Ctrl Mem MUX 7 Sign Ext d +7 ALU v Data C D-Mem v ƮMƮM Ʈ Reg Ʈ ALU Ʈ clk Ʈ Reg ƮMƮM 33 / 54

36. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Single-Cycle Implementation Example: Ʈ M = 200 picoseconds Ʈ ALU = 100 picoseconds Ʈ Adder = 100 picoseconds Ʈ Reg = 50 picoseconds Fastest Clock? 9:28 AM Load Immediate/ALU: Ʈ clk > Ʈ M + 2 Ʈ Reg + Ʈ ALU Conditional Jump: Ʈ clk > Max 2 Ʈ Adder Ʈ M + Ʈ Reg + Ʈ ALU Load Memory: Ʈ clk > 2 Ʈ M + 2 Ʈ Reg + Ʈ ALU Store Memory: Ʈ clk > 2 Ʈ M + Ʈ Reg + Ʈ ALU TypeDelay LI / ALU400 ps LD600 ps ST550 ps Cond. Jump350 ps Ʈ clk = ps  GHz 34 / 54

37. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Multicycle Implementation  Instructions take different number of clock cycles  Functional units can be shared within the execution of a single instruction 9:28 AM Data A Data B Register File Data C Reg A (Read) Reg B (Read) Reg C (Write) IR MDR X Y Result ALU Memory Addr Data PC 35 / 54

38. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Multicycle Implementation  Some registers are not visible to the programmer 9:28 AM Data A Data B Register File Data C Reg A (Read) Reg B (Read) Reg C (Write) IR MDR X Y Result ALU Memory Addr Data PC 4 SignExtend Shift Left 2 Exercise: Can you do all the previous instruction here? 36 / 54

39. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Multicycle Implementation  Some registers are not visible to the programmer 9:28 AM Data A Data B Register File Data C Reg A (Read) Reg B (Read) Reg C (Write) IR MDR X Y Result ALU Addr Data PC 4 SignExtend Shift Left 2 01 0123 01 01 01 Memory 01 37 / 54

40. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Multicycle Datapath Operation  Fetch Instruction 9:28 AM CLK PC 0 ƮMƮM 3401000A Y MUX 2 (Add) ALU Ctrl PC MUX X MUX 4 ALU Ʈ ALU 0 IR LD Mem Rd PC LD Ʈ clk 1 IR Mem Out 38 / 54

41. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Multicycle Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands 9:28 AM CLK PC 4 0 2 3401000A (LLI R 1, 10) 130110 RsRs RtRt Immediate Reg A Sel 0 X LD 0 Data A Ʈ Reg X 10 Sign Ext Ʈ clk IR LD Mem Rd IR Mem Out 39 / 54

42. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Multicycle Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands  Execute it 9:28 AM CLK PC 4 IR 3401000A (LLI R 1, 10) 130110 RsRs RtRt Immediate 3 X 0 Y MUX ALU Ctrl X MUX ALU 2 2 (Add) 10 Ʈ ALU Result LD Result Ʈ clk X LD 40 / 54

43. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Multicycle Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands  Execute it 9:28 AM CLK PC 4 IR 3401000A (LLI R 1, 10) 130110 RsRs RtRt Immediate 4 Result LD Result Ʈ clk 10 C MUX Reg C Write Ʈ Reg Ʈ clk Reg C Sel 1 41 / 54

44. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Multicycle Datapath Operation CLK PC Mem Rd Mem Out IR LD IR ALU Ctrl ALU PC LD Reg A Sel Data A Sign Ext 04 3401000A 3401000A (LLI R 1, 10) 2 (Add) 10 0 0 X LD X 10 0 Result LD Result 10 4 IR  M[PC] PC  PC + 4 X  Reg[IR[25:21]] Rs R  X+IR[15:0] Immediate Reg[IR[20:16]]  R Rt. 130110 RsRs RtRt Immediate 2 (Add) Reg C Sel 1 Reg C Write 42 / 54

45. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Multicycle Datapath Operation CLK PC Mem Rd Mem Out IR LD IR ALU Ctrl ALU PC LD Reg A Sel Data A Sign Ext i Add result X LD X Result LD Result result i+4 IR  M[PC] PC  PC + 4 X  Reg[IR[25:21]] Y  Reg[IR[20:16]] R  PC+IR[16:0]] ALU Operation: R  X op Y R  X op IR[16:0] Opcode Reg C Sel Rd Reg C Write i+4 instruction i+4+disp Add value Rs Selection Rs Reg[IR[15,11]]  R MDR  Mem[R] Mem[R]  Y Rt LD Operation: Reg[IR[20:16]]  MDR.

46. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Multicycle Implementation Example: Ʈ M = 200 picoseconds Ʈ ALU = 100 picoseconds Ʈ Adder = 100 picoseconds Ʈ Reg = 50 picoseconds Fastest Clock? 9:28 AM Load Immediate/ALU: 4 Clocks Load Memory: 5 Clocks Store Memory: 4 Clocks TypeInstr. Mix LI / ALU52% LD25% ST10% Cond. Jump13% Ʈ clk =  GHz Conditional Jump: 3 Clocks On Average: CPI = Instr. Exec. Time = ps 44 / 54

47. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Control Implementation 9:28 AM Control Unit CU Data Processing Unit DPU or Datapath Datapath Control Signals: ALU Operation, MUX Selection, Memory Rd/Wr, etc Datapath Control Signals: ALU Operation, MUX Selection, Memory Rd/Wr, etc Datapath Status Signals: IR Fields, ALU Flags Datapath Status Signals: IR Fields, ALU Flags 45 / 54

48. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Control Implementation  Hardwired ●Standard Logic Components ●Fast ●Not Flexible, i.e. Difficult to Change Control Operation  Microprogrammed ●Memory-Based ●Speed Function of Memory (slower than hardwired) ●Flexible Design 9:28 AM 46 / 54

49. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Control Implementation  Hardwired ●Finite State Machine 9:28 AM State Register Combinational Control Logic Datapath Control Outputs Datapath Control inputs 47 / 54

50. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Microprogrammed Control Implementation  Each Line in the Micro- Program Executes Micro- Operations (in 1 Clock)  Fetch, Decode, Execute Cycle 9:28 AM ALU Operation, MUX Selection, Memory Rd/Wr, etc 48 / 54

51. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Microprogram Control Unit Datapath Control Signals: 9:28 AM 49 / 54

52. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Microprogram Control Unit 9:28 AM C 19 C 0 1 Opcode Funct Z Cy etc Adder 50 / 54

53. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Microprogram Control Unit  Fetch Instruction 9:28 AM IR  M[PC] PC  PC + 4 51 / 54 0 1 μPC M 0 S 1 S 0 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0

54. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Microprogram Control Unit  Decode / Get Operands 9:28 AM IR  M[PC] PC  PC + 4 X  Reg[IR[25:21]] Y  Reg[IR[20:16]] R  PC+4*IR[15:0]] Opcode = 0 Funct = 100010 = 8 52 / 54 0 1 0 0 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 μPC M 0 S 1 S 0 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0

55. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Microprogram Control Unit  Execute Instruction 9:28 AM IR  M[PC] PC  PC + 4 X  Reg[IR[25:21]] Y  Reg[IR[20:16]] R  PC+4*IR[15:0]] R  X – Y Opcode = 0 Funct = 100010 = 8 53 / 54 1 0 0 0 1 8 9 0 0 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 μPC M 0 S 1 S 0 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 1 1 0 1 1 0 0 1 0 1

56. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Microprogram Control Unit  Execute Instruction 9:28 AM IR  M[PC] PC  PC + 4 X  Reg[IR[25:21]] Y  Reg[IR[20:16]] R  PC+4*IR[15:0]] R  X – Y Opcode = 0 Funct = 100010 = 8 54 / 54 1 0 0 0 1 8 9 0 0 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 μPC M 0 S 1 S 0 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 0 0 1 0 0 1 0 0 1 1 0 1 0 1 1 0 1 Reg[IR[15,11]]  R 1 1 0 1 1 0 0 1 0 1

57. Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Chapter 5