1. Claudia-Elisabeth Wulz Anton Taurok Institute for High Energy Physics, Vienna Trigger Internal Review CERN, 6 Nov. 2001 GLOBAL TRIGGER

2. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz2 URL’s and Publications This talk may be found at: http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalTrigger/trans/wulz_IntRev_nov01.ppt General information about the Global Trigger and the Global Muon Trigger is available at: http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalTrigger http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalMuonTrigger The following papers have been published: C.-E. Wulz: “Concept of the First Level Global Trigger for the CMS Experiment at LHC”, Nucl. Instr. Meth. A473/3 (2001) 227-238 A. Taurok et al: “Implementation and Synchronization of the First Level Global Trigger for the CMS Experiment at LHC”, Nucl. Instr. Meth. A473/3 (2001) 239-255

3. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz3 Board Layout of the Global Trigger Processor PSB (Pipeline Synchronizing Buffer)Input synchronization (6 boards including GMT) GTL (Global Trigger Logic) Logic calculation (1-2 boards) FDL (Final Decision Logic) L1A decision (1 board) TCS (Trigger Control System Module)Trigger Control (1 board) NEW: L1A (Level-1 Accept Module)Delivery of L1A (1 board) TIM (Timing Board)Timing (1 board) GTFE (Global Trigger Frontend) Readout (1 board)

4. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz4 Global Trigger 9U Crate

5. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz5 New: GMT solution with 1 logic board

6. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz6 Main Global Trigger Rack Monitoring PC Private PC

7. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz7 Auxiliary Global Trigger Rack In “official” version of rack layout (http://cmsdoc.cern.ch/~wsmith/USC55_racks.html) two racks were foreseen for Global Trigger and Global Muon Trigger. The auxiliary Global Trigger Rack replaces the GMT rack, since the GMT is now entirely housed in the main Global Trigger rack. The proposed location of the main rack is E04 and of the auxiliary rack is E03 on the lower floor of zone 6. The auxiliary rack may house subsystem specific control modules, emulators and other units still to be defined.

8. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz8 Global Trigger Progress and Milestones  Milestone March 2002: System Test This includes the backplane, the PSB-6U, GTL-6U, FDL-9U and TIM-9U. The GTFE and the GMT are not included. 4Backplane-6U: Prototype available 80 MHz GTL-plus signals, Channel Links 2mm connectors, 160 pin VME connectors Power Supplies: +5V, +3.3V, +2.5V, +1.8V

9. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz9 PSB-6U 4PSB-6U: available. Channel Link receivers used. 1 Sync Chip for 2 channels. Monitoring of all Input bits for every BX Synchronisation checks for every BX

10. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz10 PSB-9U Memories inside FPGA for Readout: 3-5 bx read by a L1A

11. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz11 GTL-6U Automatic chip design and setup procedure developed. Layout for a 20 channel GTL (4 , 4 isol. e/ , 4 central jets, 4 fwd jets,  E T, E T miss, 8 jet multiplicities; other quadruplets can be connected alternatively for tests) is currently being finished. 1020-pin Altera FPGA 20k400E included for evaluation. The layout of a conversion board to be used later in final 9U-crate is ready. It contains also memories in FPGA’s to send simulated test data to the GTL-6U board. Redefinition of jet input groups necessary for GTL-9U.

12. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz12 GTL-9U Redefinition of jet input groups necessary

13. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz13 FDL-9U Design with 8 final OR’s in progress. Some delay to be expected. Monitoring of all algorithm and L1A bits Prescaling of all algorithms Trigger Mask 8 L1A’s in parallel for partition modes

14. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz14 TIM-9U The schematic design is in progress. The board contains a TTCrx chip and provides all timing signals for the GT crate. It will be used also in the Drift Tube Track Finder crates. An FPGA provides all necessary test functions to run the crate without the central TTC clock. It simulates also L1A requests for monitoring or to test the readout chain.

15. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz15 Global Trigger Progress and Milestones  Milestone July 2002: TCS-9U ready TCS-9U: The main functions are defined but the design is still open for additional requests (calibration logic etc.) Trigger Partitions: The maximum number of subsystems is fixed (32). A preliminary agreement about the output to the DAQ Event Manager is has been reached. The input format of Fast Signals should be fixed soon. 5 coded bits per subsystem, sent as LVDS parallel data, are proposed. DSUB15 connectors are proposed. The TCS board provides data for the standard TTCvi as well as for a ”CMS- TTCvi”, but different interface boards are required. L1A driver module to be used with CMS-TTCvi has been conceived.

16. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz16 TCS-9U environment

17. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz17 L1A Driver Board

18. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz18 Global Trigger Progress and Milestones  Milestone October 2002: 9U backplane ready The design with the GTLp 80 MHz and Channel Links is in progress.  Milestone June 2003: Complete GT prototype available Integration tests possible from this date. GTFE-9U: Conceptual design of readout board done.  Milestone July 2004: 12-channel PSB-9U available PSB-9U: Conceptual design done. Will have memories inside FPGA’s.  Milestone Nov. 2004: Complete GT available Includes GTL-9U module with all 32 input channels (4 , 4 isol. e/ , 4 non-isol. e/ , 12 jet channels,  E T, E T miss, 8 jet multiplicities). The Global Muon Trigger will have been completed by Nov. 2003.

19. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz19 Input / Output of Trigger Objects Muons from RPC, DT, CSC regional triggers to Global Muon Trigger –The muons are transferred as 40 MHz parallel LVDS signals using 68-pin SCSI-3 connectors and screened round twisted pair cables (type to be defined). Cable lengths less than 10 m. Calorimeter trigger objects from the Global Calorimeter Trigger to GT-PSB boards and MIP/ISO bits from the Global Calorimeter Trigger to the Global Muon Trigger – The trigger objects are transferred by 28-bit Channel Links. Redefinition of jet groups is necessary. Data rate is 40 MHz. To minimize latency the links run at 80 MHz and send each word twice. A skew clear cable will be used, the connectors are not yet defined. Cable lengths less than 5 m. Muon trigger objects from the Global Muon Trigger to the Global Trigger – The muons are transferred in parallel on the backplane.

20. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz20 Input / Output of L1A and Control Signals The Global Trigger exchanges signals with the subsystem partitions, the TTC and DAQ systems. FAST SIGNALS from 32 subsystem partitions – 5 parallel LVDS signals carry coded status and/or command words – Cables and connectors to be defined L1A and Commands (B-Go) to 32 TTCvi – 32 cables. Details will depend on chosen TTCvi option. 2 serial links to DAQ PC – 1 S-link to DAQ readout, 1S-link to Event Manager (standard defined by DAQ) TTC – 1 optical link

21. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz21 Latency, Installation and Commissioning The latency for the Global Trigger is still 8 bx. Internal checks within the system can all be done on the surface, even in the laboratory. Checks needing input from subsystems can also be done on the surface, but timing should be as close to the real one as possible (programmable delays on input, …). Final synchronzation needs to be done in the underground area. Time needed for commissioning will depend also a lot on other subsystems!

22. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz22 Status and plans of software Use cases have been collected for the Global Trigger and Global Muon Trigger (and the Drift Tube Track Finder). A draft internal note “On-line Software Requirements for the GT, the GMT and the DTTF” can be found at: http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalTrigger/notes/SWreq.doc Transparencies have been shown in Sept. 2001 and can be found at: http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalTrigger/trans/ wulz_swreq_sep01.ppt We plan to start to develop needed software next year, in collaboration with the CMS-wide effort.

23. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz23 GT and GMT Manpower  System Engineer: A. Taurok  CERN Doctoral Student: H. Sakulin (Logic and hardware design of GMT, simulation studies)  Technicians: (shared with DTTF and other activities) H. Bergauer, M. Padrta, K. Kastner (in Vienna) Ch. Deldicque (at CERN)  Physicists: M. Fierro, A. Jeitler, C.-E. Wulz (mainly working on GT/GMT) N. Neumeister, P. Porth, H. Rohringer, L. Rurua (partly working on other activities) L. Boldizsar (GT simulation, about 4 months per year in 2001 and 2002)

24. Internal Review, 6 Nov. 2001 Claudia-Elisabeth Wulz24 Conclusions Progress in hardware design essentially as planned Layout of GTL-6U almost ready, conversion board for 9U ready Timing module designed L1A Driver Board designed Other modules also on track (except maybe FDL) Design of TCS system updated Crate and rack layout updated Software concept (in coordination with DTTF and GMT and CMS-wide solutions) starting to be developed