1. CHAPTER 6 INTERRUPTS AND THE 8259 CHIP

2. What happens on interrupt? Micro automatically saves (on stack) the FR (flag register), IP (instruction pointer), CS (code segement register). There are 255 interrupts. The address of the appropriate ISR can be computed by multiplying the interrupt number by 4! The 4 bytes in the interrupt vector table contain CS:IP The address where the ISR is located is IP <= IP value in table + CS value in table (shifted left one nybble!) Example: CS value in table is $0001 and IP is $1820 then ISR routine starts at $11820

3. Interrupt Vector Table

4. 8088 Interrupt List

5. Hardware Versus Software Interrupts INTR (pos level sensitive) and NMI (posedge sensitive) INT is command that causes software interrupt. Also, have EXCEPTIONS (SWI that happens automatically w/o INT cmd) If we only have one INTR pin, does that mean we can only have one kind of interrupt? NO. 8259 chip will allow us to have up to 8 AND if we use nine 8259 chips we can have up to 64!

6. Condition Codes (Status) Register

7. ISR Addresses

8. 8259 Programmable Interrupt Controller

9. 8259 Programmable Interrupt Controller Block Diagram

10. Addresses for 8259 ICWs

11. ICW1 and ICW2 Formats

12. INT Numbers

13. ICW3 and ICW4 Formats

14. Finding ICWs for a 8259

15. Addresses for 8259 OCWs

16. OCW Format for the 8259

17. Enabling IR0 thru IR7

18. Issuing the EOI to 8259 Chip

19. 8259 Port Addresses in IBM PC/XT Computer

20. PC/XT I/O Address Map

21. IBM PC/XT hardware Interrupts

22. IBM PC/XT Initialization of 8259

23. What happens on interrupt?

24. PC/XT Sources of Hardware Interrupt

25. PC/XT Sources of NMI Interrupt

26. PC/XT Port Uses

27. What caused the NMI?

28. Ch 6 Problems (part1)

29. Ch 6 Problems (part 2)

30. Ch 6 Problems (part 3)