1. ELEN 468 Lecture 271 ELEN 468 Advanced Logic Design Lecture 27 Gate and Interconnect Optimization

2. ELEN 468 Lecture 272 MOS Transistor Technology p substrate n well nnpp source drain gate g d s s d g

3. ELEN 468 Lecture 273 I-V Characteristics Cutoff region V gs < V t I ds = 0 Linear region V gs > V t, 0 < V ds < V gs -V t I ds = B[(V gs -V t )V ds – V 2 ds /2] Saturation region V gs > V t, 0 < V gs -V t < V ds I ds = B(V gs -V t ) 2 /2 B = a W/L g d s V ds I ds

4. ELEN 468 Lecture 274 Switching Characteristics d inout V dd V ds I ds t fall t delay t t V in V out

5. ELEN 468 Lecture 275 Falling and Rising Procedure out V dd out V dd out V dd out V dd Input risingInput falling Saturation Linear

6. ELEN 468 Lecture 276 Falling Time Falling time = t1 + t2 t1 = V out drops from 0.9V dd to V dd -V t t2 = V out drops from V dd -V t to 0.1V dd Falling time = rising time ≈ k C / (B V dd ) Delay ≈ Falling time / 2

7. ELEN 468 Lecture 277 Cascaded Inverters p: stage ratio size i+1 = p ● size i R i+1 = R i / p C i+1 = p ● C i 123 k CLCL

8. ELEN 468 Lecture 278 Delay of Cascaded Drivers Delay between stage i and i+1 R i ● C i+1 = p ● R i ● C i Total delay from stage 1 to stage k pR 1 C 1 + pR 2 C 2 + … + pR k-1 C k-1 + R k C L = pR 1 C 1 + pR 1 C 1 +…+ pR 1 C 1 + R 1 C L / p k-1 = (k-1)pR 1 C 1 + R 1 C L / p k-1

9. ELEN 468 Lecture 279 Minimum Delay Stage Ratio A = (k-1)●R 1 ●C 1, B = R 1 ●C L t = A●p + B●p 1-k Let derivative t’ = 0 A + (1-k)●B●p -k = 0 p k = (k-1) ●B/A = C L / C 1 p = [C L / C 1 ] 1/k

10. ELEN 468 Lecture 2710 Optimal Number of Stages C L = C 1 p k k = ln(C L /C 1 ) / ln p t = k●p●R 1 ●C 1 = (ln (C L /C 1 ) / ln p – 1)●p●R 1 ●C 1 Delay t reaches minimum when p ≈ 2.72

11. ELEN 468 Lecture 2711 Driver Sizing

12. ELEN 468 Lecture 2712 Combine Buffering and Driver Sizing Directly? Min delay

13. ELEN 468 Lecture 2713 Impact To Previous Stage Current stagePrevious stage Small load Large load Large delay Small delay CdCd

14. ELEN 468 Lecture 2714 Input Load Penalty Penalty = delay of min delay buffer chain driving C d Min buffer CdCd

15. ELEN 468 Lecture 2715 Driver Sizing Considering Impact to Previous Stage Current stage Previous stage Small load Large load Large delay Small delay CdCd Large penalty

16. ELEN 468 Lecture 2716 Driver Sizing in Van Ginneken’s Algorithm Treat the buffer chain as a part of the net Length = 0 Run van Ginneken’s algorithm with fixed driver and min sized buffer

17. ELEN 468 Lecture 2717 Dependence on Steiner Tree Timing critical

18. ELEN 468 Lecture 2718 Rectilinear Steiner Minimum Tree Given a signal net, find the best tree connecting them Minimize wire area Wire area implies Cost Capacitive load  delay Find Steiner minimum tree Spanning tree Steiner tree Steiner node

19. ELEN 468 Lecture 2719 Hanan Grid and Hanan Theorem Hanan grid Draw vertical and horizontal lines through all pins Hanan Theorem There is always a Steiner minimum tree on Hanan grid

20. ELEN 468 Lecture 2720 Iterative 1-Steiner Algorithm In each step, add one Steiner node such that the spanning tree is minimized

21. ELEN 468 Lecture 2721 Area or Radius? Prim’s minimum spanning tree Small total wire length Long path to sinks Dijkstra’s shortest path tree Short path to sinks Large total wire length Radius: the longest source-sink path length

22. ELEN 468 Lecture 2722 Area Radius Trade-off Find a solution in middle Not too much area Not too long radius How to find an ideal point?

23. ELEN 468 Lecture 2723 Prim’s and Dijkstra’s Algorithms d(i,j): length of edge (i, j) p(i): length of path from source to i Prim: min d(i,j) Dijkstra: min d(i,j) + p(i) d(i,j) p(i) i j

24. ELEN 468 Lecture 2724 The Prim-Dijkstra Trade-off Prim: add edge minimizing d(i,j) Dijkstra: add edge minimizing p(i) + d(i,j) Trade-off: c●p(i) + d(i,j) for 0 ≤ c ≤ 1 When c=0, trade-off = Prim When c=1, trade-off = Dijkstra

25. ELEN 468 Lecture 2725 Spanning Tree → Steiner Tree

26. ELEN 468 Lecture 2726 Rectilinear Steiner Arborescence (RSA) Every source-sink path is the shortest Minimum total wire length

27. ELEN 468 Lecture 2727 RSA Heuristic Assume all sinks in first quadrant Initially, each sink is a subtree Iteratively merge or grow subtrees toward the source

28. ELEN 468 Lecture 2728 RSA Example Merge Grow

29. ELEN 468 Lecture 2729 Merging Rule In RSA Heuristic Iteratively Find subtrees rooted at p and q maximizing min(x p, x q ) + min (y p, y q ) Merge them to a new subtree rooted at r = (min(x p, x q ), min (y p, y q ))

30. ELEN 468 Lecture 2730 RSA Diagonal Line Sweep 5 6 4 3 1 2

31. ELEN 468 Lecture 2731 Buffered A-Tree