2. 2 4 Dec 2008C+C Crate Layout CC Master TCLKA TCLKB RX17 TX17 RX18 TX18 RX19 TX19 RX20 TX20 (wired-OR) Bunch Clock FE Clock (99MHz) Trig (Start) EncClock BunchClock Spare Reset Command Veto Status CC Slave Timing Receiver Ext Clock Ext Trig = Signal Source CC Slave

3. 3 4 Dec 2008C+C CC Master/Slave CC RTMDAMC2 RTM Conn. 8x/16x RJ45 Optional for external signals FE Clock (99MHz) Command Veto Status 4Mpix/crate OKAY Will design for 16 channels, but 1 st implementation can be 8 channels Backplane CC FMC provides options e.g. signal conditioning input Veto

4. 4 4 Dec 2008C+C Timing Receiver Requests Timing Receiver Requests:Timing Receiver Requests: –Local oscillator for stand alone test operation –Capability for stand-alone backplane signals generation (we could contribute firmware??)(we could contribute firmware??) –Discussion needed regarding encoding of telegram Any way around avoiding distributing 108MHz?Any way around avoiding distributing 108MHz? Can we revisit TR using our 99MHz?Can we revisit TR using our 99MHz? –External Inputs (LVDS/LVTTL) (Front-panel or RTM?) – min required 4? ClockClock TriggerTrigger LaserLaser SpareSpare –Required telegrams Start Train (>15ms before train)Start Train (>15ms before train) Train Number (incrementing)Train Number (incrementing) End Train (?ms after/before?)End Train (?ms after/before?) Bunch Pattern IndexBunch Pattern Index Bunch Pattern Content (actually distributed by Control – not on CC Command line)Bunch Pattern Content (actually distributed by Control – not on CC Command line) –EncClock protocol? We might suggest Manchester, but is the half BW a problem?We might suggest Manchester, but is the half BW a problem? Separate clock + data linesSeparate clock + data lines –BunchClock Must be continuous (and no phase changes)Must be continuous (and no phase changes) –Is the RTM in any way similar to the DAMC2 (e.g. is the clock on the same pin)? –APD/PETRA Local logicLocal logic –Generate bunch clock from orbit trigger input

5. 5 4 Dec 2008C+C Stand Alone Mode WITHOUT Timing Receiver (no external inputs) Generate Bunch ClockGenerate Bunch Clock Generate FEE Clock (99MHz)Generate FEE Clock (99MHz) Generate Start/EndGenerate Start/End –(is in Bunch clock steps) Generate Output Trigger for external deviceGenerate Output Trigger for external device –Programmable delay wrt Start Signal (in BC steps + ~1ns steps) –Front-panel outputs, using an FMC. Generate ResetGenerate Reset Generate VetoGenerate Veto SequencerSequencer FEE Internal CalibrationFEE Internal Calibration –Must set internal delays wrt Start Signal (sub BC step)

6. 6 4 Dec 2008C+C Timelines NOW: Discussions with RAL re RTM projectDiscussions with RAL re RTM project VETO issues (e.g. separate crate)VETO issues (e.g. separate crate) Finalise designFinalise design CC hardware requirementsCC hardware requirements –xTCA Crate (~5 slot job) –>= 1 TR board + working firmware –>= 1 DAMC2 + working firmware +2 weeks Distribute to FEE+TB+TR+FEA groupsDistribute to FEE+TB+TR+FEA groups +2 weeks: assimilate feedback = FINAL designassimilate feedback = FINAL design + 1 week Firmware development with eval board of telegram encoder/decoderFirmware development with eval board of telegram encoder/decoderSeptember RAL starts RTM designRAL starts RTM design TR available (2 for WP76, later 1 to UCL)TR available (2 for WP76, later 1 to UCL) TB/CC meetingTB/CC meeting –CC design review (freeze) –Prioritised list of telegrams for TR group. WP76 gets Crate+ADC+TRWP76 gets Crate+ADC+TR –Control software (i.e. configure TR) + ADC firmware work –Firmware development overlap with CC (invitation to UCL) January DAMC2DAMC2