1. EE2420 – Digital Logic Summer II 2013 Hassan Salamy Ingram School of Engineering Texas State University Set 12: Multiplexers, Decoders, Encoders, Shift Register Class book: Chapter 6 Online book: chapter 8

2. Multiplexer  In its standard form, a multiplexer takes an N-bit control input to determine which of 2 N data inputs will be passed to its single output.  In other words, a multiplexer selects one of multiple inputs  Functions may be implemented by using a combination of the control inputs and data inputs. 2

3. (a) Graphical symbol f s w 0 w 1 0 1 (b) Truth table 0 1 f f s w 0 w 1 (c) Sum-of-products circuit s w 0 w 1 A 2-to-1 multiplexer 3

4. f s 1 w 0 w 1 00 01 (b) Truth table w 0 w 1 s 0 w 2 w 3 10 11 0 0 1 1 1 0 1 fs 1 0 s 0 w 2 w 3 f (c) Circuit s 1 w 0 w 1 s 0 w 2 w 3 (a) Graphic symbol A 4-to-1 multiplexer. 4

5. 0 w 0 w 1 0 1 w 2 w 3 0 1 f 0 1 s 1 s Using 2-to-1 multiplexers to build a 4- to-1 multiplexer 5

6. w 8 w 11 s 1 w 0 s 0 w 3 w 4 w 7 w 12 w 15 s 3 s 2 f A 16-to-1 multiplexer. 6

7. x 1 0 1 x 2 0 1 s y 1 y 2 x 1 x 2 y 1 y 2 (a) A 2x2 crossbar switch (b) Implementation using multiplexers s A practical application of multiplexers 7

8. (a) Implementation using a 4-to-1 multiplexer f w 1 0 1 0 1 w 2 1 0 0 0 1 1 1 0 1 fw 1 0 w 2 1 0 (b) Modified truth table 0 1 0 0 1 1 1 0 1 fw 1 0 w 2 1 0 f w 2 w 1 0 1 f w 1 w 2 w 2 (c) Circuit Synthesis of a logic function using multiplexers 8

9. w 3 w 3 f w 1 0 w 2 1 (a) Modified truth table (b) Circuit 0 0 0 1 1 1 0 1 fw 1 0 w 2 1 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 3 9 Implementation of the three-input majority function using a 4-to-1 multiplexer.

10. (a) Truth table 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 2 w 3  w 2 w 3  f w 3 w 1 (b) Circuit w 2 Three-input XOR implemented wit 2-to- 1 multiplexers 10

11. f w 1 w 2 (a) Truth table (b) Circuit 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 3 w 3 w 3 w 3 w 3 Three-input XOR function implemented with a 4-to-1 multiplexer 11

12. 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 (b) Circuit 0 1 f w 1 w 2 w 3 w 2 w 3 + f w 3 w 1 w 2 (b) Truth table 12 The three-input majority function implemented using a 2-to-1 multiplexer.

13. What is a Demultiplexer (DEMUX)?  A DEMUX is a digital switch with a single input (source) and a multiple outputs (destinations).  The select lines determine which output the input is connected to.  DEMUX Types  1-to-2 (1 select line)  1-to-4 (2 select lines)  1-to-8 (3 select lines)  1-to-16 (4 select lines) 13 Demultiplexer Block Diagram Select Lines Input (source) Outputs (destinations) 2N2N 1 N DEMUX

14. Typical Application of a DEMUX 14 Single Source Multiple Destinations Selector D0 D1 D2 D3 X DEMUX BASelected Destination 00B/W Laser Printer 01Fax Machine 10Color Inkjet Printer 11Pen Plotter B/W Laser Printer Color Inkjet Printer Pen Plotter Fax Machine

15. Decoder  In its standard form, a decoder takes an N-bit input and outputs 2 N functions, each of which is active for exactly one input combination.  In other words, a decoder outputs the minterms of the inputs (or with inverted outputs, the maxterms)  Functions may be implemented with the addition of a single extra gate. For example, an OR gate may be used to combine minterms for a sum-of-products implementation or an AND gate may be used to combine maxterms for a product-of-sums implementation. 15

16. 0 w n1– n inputs En Enable 2 n outputs y 0 y 2 n 1– w An n-to-2 n binary decoder. 16

17. A 2-to-4 decoder. 0 0 1 1 1 0 1 y 0 w 1 0 w 0 (c) Logic circuit w 1 w 0 xx 1 1 0 1 1 En 0 0 0 1 0 y 1 1 0 0 0 0 y 2 0 1 0 0 0 y 3 0 0 1 0 0 y 0 y 1 y 2 y 3 w 0 y 0 w 1 y 1 y 2 y 3 (a) Truth table(b) Graphical symbol 17

18. w 2 w 0 y 0 y 1 y 2 y 3 w 0 En y 0 w 1 y 1 y 2 y 3 w 0 y 0 w 1 y 1 y 2 y 3 y 4 y 5 y 6 y 7 w 1 A 3-to-8 decoder using two 2-to-4 decoders. 18

19. A 4-to-16 decoder built using a decoder tree. w 0 En y 0 w 1 y 1 y 2 y 3 y 8 y 9 y 10 y 11 w 2 w 0 y 0 y 1 y 2 y 3 w 0 En y 0 w 1 y 1 y 2 y 3 w 0 y 0 w 1 y 1 y 2 y 3 y 4 y 5 y 6 y 7 w 1 w 0 y 0 w 1 y 1 y 2 y 3 y 12 y 13 y 14 y 15 w 0 En y 0 w 1 y 1 y 2 y 3 w 3 19

20. w 1 w 0 w 0 En y 0 w 1 y 1 y 2 y 3 w 2 w 3 f s 0 s 1 1 20 A 4-to-1 multiplexer built using a decoder.

21. 21 Decoders: Designing Logic Circuits F =  m(0,2)

22. Sel 2 1 0 2 m 1– Address Read d 0 d n1– d n2– m -to-2 m decoder 0/1 Data a 0 a 1 a m1– 22 A 2 m x n read-only memory (ROM) block.

23. 2 n inputs w 0 w 2 n 1– y 0 y n1– n outputs 23 A 2 n -to-n binary encoder.

24. 0 0 1 1 1 0 1 w 3 y 1 0 y 0 w 1 w 0 0 0 1 0 w 2 0 1 0 0 w 1 1 0 0 0 w 0 0 0 0 1 y 0 w 2 w 3 y 1 (a) Truth table 24 A 4-to-2 binary encoder.

25. 4-bit Data Shifter  Data Shifter  A combinational logic shifter is a device that produces an output obtained by shifting its input  Right Shift: The Most Significant bit is called the fill bit and the Least Significant bit is called the spill bit  Left Shift: MSB is the spill bit – LSB is the fill bit  Processes:  Logical Shift => a logic zero is inserted in the fill position  Arithmetic => the sign bit is extended in a right shift  End-around [or rotate] 25

26. 4-bit Logical Shifter Problem Statement  Step 1: Clear Problem Statement  Design and implement a 4-bit logical shifter that has 4-bit input “A”, 4-bit output “S”, and 1-bit controls X and Y where: 26

27. 4-bit Logical Shifter Conceptualization  Step 2: Conceptualization  This 4-bit shifter can be represented by the black-box model below with the associated Output Table 27

28. 4-bit Logical Shifter Solution/Simplification  Step 3: Solution/Simplification  The output table, with it’s different terms and exact duplication of bit values - - Should suggest a multiplexer  The logic functions describing the assignment of the values is: 28

29. 4-bit Logical Shifter Realization and Verification  Step 4: Realization  Those 4 output values can be implemented using four 4-to- 1 mux’s as follows:  Step 5: Verification  Lab time! - - Does it really do what you designed it to do?  Return to that K-map/Truth table and be sure! 29