1. MICAS Department of Electrical Engineering (ESAT) Design-In for EMC on Digital ICs for Automotive electronics April 18th, 2006 Junfeng Zhou Promotor: Prof. Wim Dehaene KULeuven ESAT-MICAS

2. MICAS Department of Electrical Engineering (ESAT) 1. Introduction 2. Logic family comparison and selection 1. Comparison of different low noise logic families with SCMOS 2. Improved structure based on CSL logic – E-CSL 3. Conclusion 3. A Low noise power supply technique – EMI regulator 1. Continuous time mode 2. Stability analysis 3. Transfer function analysis 4. Implementation 5. Conclusion Outline

3. MICAS Department of Electrical Engineering (ESAT) Part I: Introduction Electro-Magnetic Interference (EMI) and radiated emission have become a major problem for automotive electronics, Most of them are due to power and ground fluctuation. Although the detailed calculation of EMI noise is rather difficult, we can use the di/dt as the index, since the current loop contributes the EMI.

4. MICAS Department of Electrical Engineering (ESAT) Part 2: Logic Family Comparison SCMOS PNMOSRSBCMOS CSL MCMLFSCL

5. MICAS Department of Electrical Engineering (ESAT) Comparison of di/dt,power and area Target : Mixed-Mode Automotive Electronics Design Key aspects : di/dt + Power + Area + Speed Ring Oscillator of 21-stages (Static + Dynamic) Current Steering Logic But there is static power !!

6. MICAS Department of Electrical Engineering (ESAT) Detailed comparison of CSL and SCMOS Note: The curve of CSL 16-bit RCA was obtained by calculating the real speed F of the circuit, given the different supply current I. CSL One-bit Adder IT is a static power problem, Switching off when standby ?

7. MICAS Department of Electrical Engineering (ESAT) Detailed comparison of CSL and SCMOS SCMOS CSL SCMOS CSL 36dB38dB

8. MICAS Department of Electrical Engineering (ESAT) Problem with CSL Mismatch sensitive, annoying for standard cells rather slow/power hungry Not full swing Matching required! M1 > M3

9. MICAS Department of Electrical Engineering (ESAT) Can we do it better ? C-CBL: sizing for optimal current balance is really difficult,process dependent CBL [Albuquerque, E.F.M.; Silva, M.M., Current-balanced logic for mixed-signal IC's] C-CBL

10. MICAS Department of Electrical Engineering (ESAT) Solution- Enhanced current steering logic Still current source basing Increase in logic level, hence increase the robustness Reduced output capacitance, hence the speed is increased Fig.3 E-CSL inverter Minimum size

11. MICAS Department of Electrical Engineering (ESAT) Comparison of CSL, C-CBL, ECSL and SCMOS Fig.5 di/dt vs. frequencyFig.4 power vs. frequency Ring Oscillator of 21-stages

12. MICAS Department of Electrical Engineering (ESAT) di/dt performance vs. process variation Fig.6 di/dt vs. process corner MAX di/dt change MIN di/dt change Ring Oscillator of 21-stages

13. MICAS Department of Electrical Engineering (ESAT) Conclusion of Low noise Logic Families Winner is E-CSL CSL,E-CSL show a smaller area per logic function for complex digital gates, Current source ensures the major di/dt reduction, Process variation sensitivity also becomes better due to the dominance of current source, E-CSL gives comparable di/dt performance with CSL, E-CSL is Faster and Less power consuming than CSL due to the lower area and lower capacitance. Static power consumption remains the challenge. Can be solved by using power down strategies, which is highly application dependent

14. MICAS Department of Electrical Engineering (ESAT) Part 3: Low Noise Power Supply design However 2 problems still remain: Static power consumption New logic family standard cell library must be designed and characterised. (large NRE cost, risk) ?? Is there any global approach ??

15. MICAS Department of Electrical Engineering (ESAT) Principles of Low Noise Power supply Diagram of Low noise power supply 1.Current source ensures the major di/dt reduction 2. Slow varying is key to EMC success 3. Do not give more current than the circuit needs, i.e. minimize the static current 1.Can be done with switched or continuous mode. 2. Continuous mode potentially has better di/dt suppression.

16. MICAS Department of Electrical Engineering (ESAT) Continuous mode Power Delivery--EMI regulator Determine the switching speed, Hence determine the di/dt Energy reservoir when slow Switching

17. MICAS Department of Electrical Engineering (ESAT) Functionality Simulation continuous time OTA feedback loop stable Idd di/dt Vcontrol VDD_input 9v9v 2 nd order under damped behaviour VDD_input Vcontrol

18. MICAS Department of Electrical Engineering (ESAT) Comparison with standard CMOS Fig.15 di/dt and FFT comparison with standard CMOS w/o CT, 3.3V only 12v supply current 12v supply current di/dt p-p = 1.0x10 7 A/s di/dt w/o CT, di/dt p-p =1.51x10 11 A/s 44dB

19. MICAS Department of Electrical Engineering (ESAT) Current pulse step response An input current step of 1 mA and 100-ps rise time was used for the calculation and simulation Can be improved if more stable ~10 2 reduction !!

20. MICAS Department of Electrical Engineering (ESAT) Coupling problem ! Cgs 1,2 ≈ Cgd1 ∆ V DD_input ∆ V bias

21. MICAS Department of Electrical Engineering (ESAT) Why new structure ? 1.Simple 2.Driving capability 3.Miller effect on compensation capacitor 4.Cascode device: decrease coupling from VDD_input to VDD provided that Vbias is biased as a low impedance node

22. MICAS Department of Electrical Engineering (ESAT) Maple calculation An input current step of 1 mA and 100-ps rise time was used for the calculation and simulation

23. MICAS Department of Electrical Engineering (ESAT) Comparison with old structure New structure Old structure ~10x reduction !!

24. MICAS Department of Electrical Engineering (ESAT) Stability analysis Approximation: p1 p2 p3 z1 dominant pole second pole High frequency pole High frequency, left half-plane zero >3 for > 72° phase margin Gain of the current source Stability ~ Caux/Ctank p4 Low impedance node

25. MICAS Department of Electrical Engineering (ESAT) Stability analysis – Simulation vs. Calculation Spectre simulation Maple calculation Raux=1.852K, Caux=20p,Ctank=100p Stability vs. Iload φ> 72 ° Iload =192.7u A Stability vs. Iload (26.7u A ~ 72m A) φ ≥ 60 ° Worst case

26. MICAS Department of Electrical Engineering (ESAT) Current TF analysis H(s)=I VDD (s)/I in (s) (i.e. di/dt attenuation) dominant pole second pole third pole High frequency zero left half-plane zero

27. MICAS Department of Electrical Engineering (ESAT) Current TF- simulation vs. calculation Spectre simulation Maple calculation Iload =80u A, Raux=1.852K, Ctank=100p Infinite Attenuation ?? Not in reality!

28. MICAS Department of Electrical Engineering (ESAT) Model revisited p1 p3 p2 z1 Cdb1 Cdb2

29. MICAS Department of Electrical Engineering (ESAT) Current TF- simulation vs. calculation Spectre simulation Maple calculation Iload =80u A, Raux=1.852K, Ctank=100p dB

30. MICAS Department of Electrical Engineering (ESAT) Maximum Attenuation Maple calculation Iload =800u A, Raux=1.852K, Ctank=100p TF vs. Caux Cut-off freq. ~ 1/Caux Large attenuation requires Large Ctank and/or small Cdb1 Cascode structure ! dB

31. MICAS Department of Electrical Engineering (ESAT) Caux/Ctank and time domain ∆V DDinput ∆VDDinput Caux = 4, 8,..20 pF ∆V DDinput ~ C aux /C tank

32. MICAS Department of Electrical Engineering (ESAT) Conclusion EMI Regulator design principles  Stability ~ C aux /C tank  Time domain ∆V DDinput ~ C aux /C tank More stable also means a larger ∆V DDinput  Current TF Cut-off freq: Gm/C aux Max. attenuation: C db /(C db +C tank )  Design for small C db Similar story possible for Gm, g m Caution should be exercised to maintain the stability of the EMI regulator while designing for higher di/dt reduction

33. MICAS Department of Electrical Engineering (ESAT) Shift register cell Determine the current peak and duration: FF Din CLK RST Out 600 [uA] × 50 × 10= 300 [mA] Then, the output current of the EMI Regulator : 30 [mA] ~ 60 [mA] 50 FF + 200 gates 10 ×5×5×

34. MICAS Department of Electrical Engineering (ESAT) EMC test chip with EMI Regulator SR1, MS-FF, No capa SR2, MS-FF, 1/2 PNMOS capa SR3, MS-FF, PNMOS capa SR4, MS-FF, PNMOS capa, PWR SR5, MS-FF, PNMOS capa, MIMC capa SR6, D-FF, No capa SR7, D-FF, 1/2 PNMOS capa SR8, D-FF, PNMOS capa SR9, D-FF, PNMOS capa, PWR SR10, D-FF, PNMOS capa, MIMC capa On-chip LDR PD On-chip Serial regulator PD SR1 RST Din CLK OUT SR2 RST Din CLK OUT SR9 RST Din CLK OUT SR10 RST Din CLK OUT GND LDO PD EMI regulator Ctank VDD_input Emergency block Power down block

35. MICAS Department of Electrical Engineering (ESAT) Top level simulation Current source simulation Frequency simulation V3v3 VDD input V3v3 VDD input

36. MICAS Department of Electrical Engineering (ESAT) Current source simulation results Current of Vbat V3v3 VDD_input Vcontrol Power down enable

37. MICAS Department of Electrical Engineering (ESAT) Frequency simulation results current of Vbat di/dt p-p =8.5x10 4 [A/s] 9x10 6 load current of digital core FFT di/dt p-p =1.8x10 9 [A/s] 7x10 3 di/dt of Vbat di/dt of V3v3 40dB (EMI regulator) + 20dB (Serial regulator)

38. MICAS Department of Electrical Engineering (ESAT) Layout of EMI regulator Area: 1mm x 1.1mm Ctank Caux Ctank C tank =100p F C aux = 20 p F Power transistors: Wp=5000 μm Lp= 1 μm (fixed) Technology : AMIS 0.35μm I3T80 Supply voltage : 12 V Output voltage : typ. 8V, min.5.5V Quiescent current : 30 μA

39. MICAS Department of Electrical Engineering (ESAT) Conclusion Current source ensures the major di/dt reduction, Low noise digital cells have the major drawback of Static power consumption, not tolerable for large digital system A Low Noise Power Supply Techniques is presented:  Control the way the current delivered to the internal digital core, hence keep the EMI under control,  Comparable reduction on di/dt noise with low noise digital cells only,  More power efficient than the low noise digital cells,  Have similar power consumption to the conventional CMOS logic,  A global approach-Can be adjusted to a wide range of chip size and power consumption level