1. George Mason University ECE 448 – FPGA and ASIC Design with VHDL ASICs vs. FPGAs ECE 448 Lecture 15

2. 2ECE 448 – FPGA and ASIC Design with VHDL FPGAs vs. ASICs ASICs FPGAs High performance Off-the-shelf Short time to the market Low development costs Reconfigurability Low power Low cost (but only in high volumes)

3. 3ECE 448 – FPGA and ASIC Design with VHDL Local Memory Global Memory ASIC Design Example – Factoring circuit/GMU

4. 4ECE 448 – FPGA and ASIC Design with VHDL 51x ASIC 130 nm vs. Virtex II 6000 Factoring/GMU 19.80 mm 19.68 mm 2.7 mm 2.82 mm Area of Xilinx Virtex II 6000 FPGA (estimation by R.J. Lim Fong, MS Thesis, VPI, 2004) Area of an ASIC with equivalent functionality

5. 5ECE 448 – FPGA and ASIC Design with VHDL Source: I. Kuon, J. Rose, University of Toronto “Measuring the Gap Between FPGAs and ASICs” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 62, no. 2, Feb 2007. ASICs vs. FPGAs

6. 6ECE 448 – FPGA and ASIC Design with VHDL 23 representative circuits implemented using FPGAs and ASICs - computer arithmetic (booth, cordic18, cordic8, etc.) - digital signal processing (rs_encoder, fir3, fir24, etc.) - communications (ethernet, mac1, atm, etc.) - cryptography (des_area, des_perf, aes, aes192, etc.) - scientific computations (molecular, raytracer, etc.) ASICs vs. FPGAs

7. 7ECE 448 – FPGA and ASIC Design with VHDL

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10. 10ECE 448 – FPGA and ASIC Design with VHDL

11. 11 ASIC Design Flow Algorithm Specification RTL Design Verilog, VHDL Logic Synthesis Layout Parasitic Extraction stdcell lib process lib Simulation LVS Simulation test vectors VCD latency throughput (post-synthesis) die area pin count latency throughp ut (post P&R) power diss Synopsys IC Compiler Cadence Encounter Synopsys Design Compiler Mentor Calibre Synopsys StarRCXT VCS Hercules Calibre PrimeTime Design Quality Reference Implementation C, C++

12. 12ECE 448 – FPGA and ASIC Design with VHDL Simplified ASIC Design Flow Synthesis Placement Clock Tree Synthesis Routing Floorplanning Timing Analysis Design for Manufacturing 31 Front-End Design Back-End Design

13. 13ECE 448 – FPGA and ASIC Design with VHDL Major ASIC Toolsets Cadence Magma

14. 14ECE 448 – FPGA and ASIC Design with VHDL Simplified ASIC Design Flow Synthesis Placement Clock Tree Synthesis Routing Floorplanning Timing Analysis Design for Manufacturing 31 Front-End Design Back-End Design Synopsys Tools Design Compiler Primetime Astro

15. 15ECE 448 – FPGA and ASIC Design with VHDL A Complete Placed and Routed Chip IP 28

16. Digital system design technologies coverage in the CpE & EE programs at GMU Microprocessors ASICs FPGAs ECE 445 ECE 447 ECE 586 ECE 681 ECE 448 ECE 511 ECE 611 ECE 431 Computer Organization Single Chip Microcomputers FPGA and ASIC Design with VHDL Digital Circuit Design Microprocessors Advanced Microprocessors Digital Integrated Circuits VLSI Design for ASICs ECE 545 Digital System Design with VHDL ECE 645 Computer Arithmetic

17. DIGITAL SYSTEMS DESIGN 1. ECE 545 Digital System Design with VHDL – K. Gaj, project, FPGA design with VHDL, Aldec/Xilinx/Altera 2. ECE 645 Computer Arithmetic – K. Gaj, project, FPGA design with VHDL or Verilog, Aldec/Xilinx/Altera/Synopsys 3. ECE 586 Digital Integrated Circuits – D. Ioannou 4. ECE 681 VLSI Design for ASICs – N. Klimavicz, project/lab, front-end and back-end ASIC design with Synopsys tools 5. ECE 682 VLSI Test Concepts – T. Storey, homework