1. 1 IMEC / KHBO June 2004 Micro-electronics SystemC Dorine Gevaert

2. 2 Part 1 : SystemC introduction Why SystemC ? Design flow mid 70’s to mid 90’s Design flow 2002 & beyond Motivation for SystemC Modeling levels and accuracy Design time is money

3. 3 Why SystemC ? Main message of the International Roadmap for Semiconductors (ITRS) “ Cost of design” is the greatest threat to the continuation of the semiconductor roadmap” AIM : reduction of design cost

4. 4 Why SystemC ? “nature of systems” change PastFuture Small block reuseIntelligent test benches Large block reuseEmbedded system-level IC implementation toolstechnology ▼ NEED of a modeling language that can support this level

5. 5 mid 70’s to mid 90’s RTL level Verilog, VHDL Gate Level Polygon Level Traditional bottom-up design replaced with HDL’s top-down design approach Design abstraction moves upwards New levels of IP emerge EDA tools move up to enable path to silicon

6. 6 Mid 90’s Specs Word/Excel EDA confronted with: –System = software running on silicon! –Serious gap between system design & RTL RTL level Verilog, VHDL Gate Level Polygon Level

7. 7 2002 & beyond RTL level SystemC Verilog, VHDL Gate Level Polygon Level Designs continue to move up to ever higher levels of abstraction SystemC bridges the gap with abstract modeling & RTL IP moves up, Again! EDA tools move up to ensure path to silicon UML, etc. unTimed Level SystemC Transaction Level SystemC

8. 8 Motivation for SystemC Major contribution : To provide a modeling frame-work for systems in which high-level functional models can be verified in a SINGLE language To improve the protection of Intellectual Property A common format for system level IP exchange and tool interoperability

9. 9 Architecture Co-Design Implement Co-Verify Verify Implement Verify SW CodeHW Design Implement Verify Design Reuse IP Code Reuse IP Software Product Hardware Environment Specify Concept to RTL to GDSII Reusable IP Integration

10. 10 Modeling levels Executable Specification Untimed Functional Model Timed Functional Model Transaction Level Model Platform Transaction Level Model Behavior Hardware Model Pin-accurate, cycle-accurate hardware Model

11. 11 Accuracy of SW/HW models Structural accuracy Timing accuracy Functional accuracy Data organization accuracy Communication protocol accuracy

12. 12 Industry Standard Architecture Co-Design Implement Co-Verify Verify Implement Verify SW CodeHW Design Implement Verify Design Reuse IP Code Reuse IP Software Product Hardware Environment Specify Concept to RTL to GDSII Reusable IP Integration HW & SW Environment Untimed models Transaction- Level Models Code RTL Models IEEE Standard

13. 13 Design flow in the past ! System Level Integration is always done last, is always on the critical path - and is always done too late for architectural redesign Module Verification Module Design Architecture Phase Q0Q1Q2Q3Q4Q5 System Level Int./Verif.

14. 14 SystemC AIM : reduction of design cost System Level Integration is done throughout the lifetime of the project Module Verification System Level Int. / Verif. Module Design Architecture Phase Q0Q1Q2Q3Q4Q5

15. 15 Part 2 : SystemC generalities Main goal of the language Enabling System Level Design What is SystemC SystemC language architecture Methodology Evolution and steering group Pro’s and contra’s

16. 16 SystemC – main goal of the new language! Specification / design refinement Incorporation of HW / SW parts in ONE language Describe executable spec Flexible HW / SW partitioning Fast simulation speed Reusability Not an entirely new language  C++ with HW extension library

17. 17 What is SystemC ? C++ extension library (classes) System Level Design Gradual refinement to gate level HW modeling in SW language Concurrency Concept of time HW data types Hierarchy Controlled by “open SystemC Initiative” www.systemc.org

18. 18 Architecture of SystemC 2.0 SystemC Scheduler Events, Dynamic Sensitivity Channels, Interfaces, Ports Elementary channels (signals, FIFOs, …) Methodology-specific and User-Defined Channels

19. 19 SystemC language architecture SystemC language architecture

20. 20 System RTL Physical HW Implementation Verification & Analysis System Level IP SW Implementation C-Compiler Soft IP Hard IP

21. 21 Hardware Software BCA RTL RTOS TF Assign ‘execution time’ HW / SW Partition Architectural mapping Abstr. RTOS Refine communication Functional decomposition UTF SystemC Refine behavior Untimed Functional Timed Functional Bus Cycle Accurate Cycle Accurate Design Exploration Performance Analysis HW/SW partitioning Task Partitioning Target RTOS/Core SpecC Esterel SDL Others Matlab

22. 22 Key to the methodology is that a design may be refined in a gradual step-wise fashion, rather than in one giant step… it need not be “all or nothing”. UTF TF UTFTF BCARTL UTFRTL Details added to portions of the system. Simulation Gradual Refinement of the Design

23. 23 Evolution of SystemC Synthesis / Place & Route etc. Advanced & Functional Verification Links to Verification and Implementation Algorithm Design System Architecture Design Space Exploration Full System Specification 1.0 2.0 2.x/3.y

24. 24 Open SystemC inititative Steering group

25. 25 Pro’s and contra’s Pro’s One common language Shorter design time Different levels of abstraction Free source code (only C++ compiler is necessary) Contra’s Rapidly evolving Still difficult for one person to go through the entire flow Strictly platform dependent

26. 26 SystemC versus VHDL SystemC Higher level of abstraction that offers a faster simulation speed Access to all of C/C++ Object orienting Programming Built-in system-level modeling capabilities It is easier to protect IP (object files instead of code) VHDL Better for RTL (Register Transfer Level) descriptions RTL descriptions have a better accuracy compared to high level descriptions More tools available

27. 27 Summary Design challenges are moving up to the System Level SystemC provides critical capabilities for modeling, design and verification for HW/SW systems SystemC offers broad commercial tool support Join OSCI to help influence the future of System-level design at: www.systemc.org

28. 28 Part 3 : SytemC design example Basic example : LFSR (Linear Feedback Shift Register) General system in SystemC Modules in SystemC Processes in SystemC LFSR SystemC description

29. 29 First design

30. 30 LFSR (Linear Feedback Shift Register)

31. 31 General System in SystemC

32. 32 Modules Definition Ports Instantiation Interconnection Hierarchy Initialization

33. 33 Basic blocks in SystemC SC_MAIN : top level of the system 3 modules : stimuli, functionality, monitor

34. 34 Module : definition Basic SystemC building blocks Break large systems in smaller pieces and insert hierarchy A module can contain : ports, local signals, local data, other modules, functions, processes and constructor Keyword SC_MODULE(name) Describe modules in 2 parts * Module definition (.h file)  Communication * Module functionality (.cpp file)  Functionality

35. 35 Module (signal-) Ports Communication with outside world 3 built-in modes : input port : SC_IN<> output port: SC_OUT<> bidirectional : SC_INOUT<> Each port has a data type f. e. : int, sc_logic, … Special module ports : input clock pin : SC_IN_CLK output clock pin : SC_OUT_CLK

36. 36 Module (signal-) Ports

37. 37 Module : inside Local data member internal calculations Processes contain functionality Constructor Keyword : SC_CTOR(name) initialization mapping member functions to processes

38. 38 Example : my_module.h

39. 39 Hierarchy : interconnect signals Keyword : SC_signal Used to interconnect module ports Used to communicate between processes

40. 40 Hierarchy : example modules inside modules

41. 41 Processes : definition Called to emulate behavior Model hardware : concurrency! No hierarchy Defined as member functions Use sensitivity lists (event driven) 2 types : SC_METHOD SC_THREAD

42. 42 SC_METHOD Can not be suspended Have a sensitivity list Combinatorial logic Fastest process Executed during initialization phase Syntax : SC_METHOD(processname); sensitivity << port (or signal) Supported for RT-synthesis (Synopsys)

43. 43 Example : SC_METHOD

44. 44 SC_THREAD Can be suspended and reactivated (wait( )) Have a sensitivity list Sequential logic Syntax : SC_THREAD(processname); sensitivity << port (or signal); Synthesis support is on-going and hot research topic !

45. 45 Example : SC_THREAD

46. 46 Sensitivity lists Used to activate processes Processes are activated due to the occurrence of an event on an element in the sensitivity list

47. 47 Process versus function Process is defined as a member function A member function becomes a process when it is mapped to a process type : SC_THREAD(my_funtion); Processes are executed in parallel Functions are executed inline

48. 48 FIRST design : LFSR

49. 49 First design : LFSR

50. 50 FIRST DESIGN : LFSR