1. E. Hazen – FNAL – 5 Apr 2004 L1CTT DFEA Motherboard / Daughterboard Design, Cost, Schedule 4

2. E. Hazen – FNAL – 5 Apr 2004 Outline ● Review of Motivation (if needed!) ● DFEM, DFEA Modules – Some Design Details – Cost Estimate / Basis – Schedule ● Stand-Alone Tester

3. E. Hazen – FNAL – 5 Apr 2004 Motivation ● Upgrade to Virtex-II or Spartan-III FPGAs ● Reduce FPGA download time from hours to minutes. ● Provide diagnostic/test access to inputs and outputs. ● Provide crate-wide SCL signal distribution for commissioning. ● Eliminate the cable front cable plant. ● Provide LED status indicators on the front panel. ● Improve daughter-board connector reliability

4. E. Hazen – FNAL – 5 Apr 2004 Current Design LVDS Inputs in Front Proposed Design All Cables in Rear

5. E. Hazen – FNAL – 5 Apr 2004 SLDB 28+CLK LVDS 1 LVDS 2 LVDS 3 LVDS 4 XC2V6000 (DDR) L1Muon L1CTT STT SLDB 28+CLK LVDS 5 LVDS 6 LVDS 7 LVDS 8 XC2V6000 (DDR) Backplane Interface FPGA DFE Backplane LVDS Timing TTL R/W Bus IsoBits New DFEA Module “baseline” (XC2V6000s) Channel-Link Receivers Channel-Link Transmitters JTAG Flash FPGA config Local bus LEDs L1Muon L1CTT STT

6. E. Hazen – FNAL – 5 Apr 2004 DFEM Layout DFE R/W Bus Serial Encoded SCL 48V Iso in/out LVDS in 1-8 Coax feed-thru for SLDB out (only 4 used) 3.3V Alternate Power LVDS out 1-4 Press-fit Hard Metric Connectors (315 total pins) Detailed Pinout in backplane spec LEDS various options for detailed status display Logic Analyzer Connector JTAG Detailed mechanical drawing exists

7. E. Hazen – FNAL – 5 Apr 2004 Hardware Design Changes ● LVDS inputs drive only one FPGA (point-to-point) – No buffers between LVDS receivers and FPGAs ● Eliminate rear transition modules... – Direct LVDS output from rear of module ● Two SLDBs on module for L1 outputs ● New DC power scheme – (48V or maybe 3.3V – under discussion) ● Full access to big FPGAs from backplane R/W bus – Complete flexibility for inject / readout of test data ● Separate programming of individual FPGAs ● SCL clock/control via LVDS on backplane

8. E. Hazen – FNAL – 5 Apr 2004 DFEA Test Features ● Extensive built-in diagnostics ● Inject arbitrary test patterns at speed ● Capture and read inputs and outputs ● Send test vectors downstream Test logic contained in main DFEA FPGAs

9. E. Hazen – FNAL – 5 Apr 2004 Manufactured Cost (M&S only estimate from parts list) ● Cost is dominated by FPGAs

10. E. Hazen – FNAL – 5 Apr 2004 DFEA Cost Summary (My estimate, not in proper WBS form!)

11. E. Hazen – FNAL – 5 Apr 2004 Phase I Schedule Prototype Development of DFEM and DFEA

12. E. Hazen – FNAL – 5 Apr 2004 Phase II Schedule Production

13. E. Hazen – FNAL – 5 Apr 2004 DFE Stand-Alone Tester ● New Backplane / Controller not ready in time to test new DFEM/DFEA ● Other infrastructure (SCL etc) not easily set up off- site ● Simple tester is a modest engineering job and is useful for production testing too

14. E. Hazen – FNAL – 5 Apr 2004 74ABT Buffers LVDS Hard Metric Backplane Connectors LVDS Channel-Link I/O Cable connectors FPGA (Virtex-II) LVDS Feed-Thru Connectors 53MHz SLDB Receiver PC Interface (Parallel port) Flash Memory JTAG SCL simulation R/W bus

15. E. Hazen – FNAL – 5 Apr 2004 Final Thoughts ● DFEM / DFEA is under control – DFEA prototype built and tested – DFEM design is simple and well-understood ● But the schedule is certainly aggressive – What can we do? ● Do some engineering in parallel ● Build a stand-alone tester ● This summer “slice test” will provide valuable experience for the comissioning ● Additional labor (Post-Doc?) needed for on-site commissioning.