1. EMBEDDED SYSTEMS ON PCI

2. INTRODUCTION EMBEDDED SYSTEMS PERIPHERAL COMPONENT INTERCONNECT The presentation involves the success of the widely adopted PCI bus and describes a higher performance next generation of I/O interconnect, called PCI Express Architecture.

3. Today’s PC has multiple local buses with different requirements.

4. PCI EXPRESS ARCHITECTURE OVERVIEW: A PCI Express multi-drop, parallel bus topology contains a Host Bridge and several endpoints. Multiple point-to-point connections introduce a new element, the switch, into the I/O system topology.

5. The multiple, similar parallel buses of today’s platform are replaced with PCI Express links with one or more lanes. PCI Express switch provides fanout capability and enables a series of connectors for add-in, high performance I/O.

6. PCI EXPRESS ARCHITECTURE:

7. The PCI Express Architecture is specified in layers: PHYSICAL LAYER LINK LAYER TRANSACTION LAYER SOFTWARE LAYER

8. CONCLUSION The PCI Express Architecture meets all of the requirements of a third generation I/O bus. Bandwidth is linearly scalable. PCI Express is software compatible with all existing PCI-based software to enable smooth integration within future systems.

9. QUERIES?