1. Local Trigger Unit for NA62 Marián Krivda 1), Cristina Lazzeroni 1), Vlado Černý 2), Tomáš Blažek 2), Roman Lietava 1)2) 1) University of Birmingham, UK 2) Comenius University, Bratislava, Slovakia 15/12/20101

2. Content General view Status of LTU production and tests Status of firmware Status of software Usage of LTU boards for Run2011 News from TTC upgrade meeting Summary 15/12/20102

3. Clock distribution and data flow 15/12/20103 LTU + TTCex LTU + TTCex LTU + TTCex LTU + TTCex 40 MHz clock source....................... TTC partition TTCrx Trigger inputs For jitter < 50 ps RMS QPLL must be used ! QPLL FEE CHOKE/ ERROR Triggers TTC Clock + Triggers Sync. card L0TP

4. LTU+TTCex+(20dB att./TTCoc) 15/12/20104 40 MHz clock source 6U VME cards 1 LTU+TTCex per detector !!! Local Trigger Unit LTU Optical transmission of A and B channel TTCex ser. data channel A ser. data channel B Trig. data from L0 processor Burst clock 31 optical outputs to FEE Detector CHOKE/ERROR LVDS (7) Warning ejection (WE) Monitoring of TTC TTCit TTCoc 1:32

5. Status of LTU production and tests First 3 LTU boards are produced – 3 faulty components LMS1583-1.5 – 2 faulty components PDU15F – 1 PCB damaged by replacing the faulty component 15/12/20105

6. Status of LTU production and tests Problems after replacement of one faulty component (2 unconnected pads and microscopic hole) 15/12/20106

7. Status of LTU production and tests Performed tests – VME FPGA connections – LTU FPGA connections – Flash Memory test – SnapShot memory test – LEDs test – Front panel connectors test 15/12/20107

8. VME BUS FRONT PANEL FLASH MEMORY stores code to be loaded into LTU FPGA VME FPGA basic "firmware" LTU FPGA LTU logic FRONT PANEL I/O connectors OSCILOSCOPE connectors LTU testing software: LTU main components Computer speaks via VME bus to VME FPGA which distributes the communication further to inner LTU parts LTU FPGA is programmed to perform LTU logic operations The LTU logic reacts to control commands from computer (by for example sending a signal from a particular point inside LTU into front panel I/O connector or sending the value back to computer via VME FPGA and VME bus Snap shot memory to provide the possibility of logging of 26 ms of the front panel data The testing software tests the communication between those main blocks Snap shot memory 15/12/20108

9. Testing software guides the operator via screen prompts like "Connect the oscilloscope to connector B" "You should see clock signal" "Press enter when ready“ Phase 0: Testing that LTU (VME FPGA) reacts to VME bus Phase 1: tests the flash memory writing and reading back random data Phase 2: loads phase 2 logic into LTU FPGA checks success of PLL clock lock tests snap shot memory by writing and reading back random data tests that data logging into snap shot memory is functional Phase 3: loads phase 3/4 logic into LTU FPGA test R/W operations to LTU FPGA Phase 4: sending various signals to specific front panel connectors and testing their presence by oscilloscope 15/12/20109 LTU testing software: Testing procedure

10. News from TTC upgrade meeting PHOTON lasers replace by OCP lasers (300 USD/pc), median life of OCP estimated to more than 88 years possible replacement of TRR1B43 by PD-LD (68 EUR/pc) or Ficer (28EUR/pc), to be qualified early 2011 new TTCex: 1. New PLL to replace obsolete VCXO 2. Standalone frequency compliant with QPLL locking range 3. Ability to turn on-off each laser individually and monitor their status 4. Available in January 2011 possible replacement of TTCrq board with TTC-FMC board, ref. design (HW + Firmware) in 2011, better connector, 2 ways (TTCrq flavor, Light flavor) 15/12/201010

11. Usage of LTUs for Run2011 Usage of PULSER (ECL) input on LTU board 15/12/201011 LTU + TTCex LTU + TTCex LTU + TTCex LTU + TTCex....................... TTC partition TTCrx QPLL FEE TTC Clock + Triggers 40 MHz clock source ECL fan-out Trigger inputs

12. Status of firmware Written some modules in Verilog (ALICE LTU is wiritten in AHDL) l0_logic (top module), pll, led, clock_check, gray_counter, gray2bin, adc, busy, ttcvi_emu, vi_fifo1024x6, l0fifo_write, l0_fifo Simulations in CADENCE 15/12/201012

13. Status of software Reminder: DIM architecture DIM servers running on VME processor in the crate DIM clients running anywhere in the world All services implemented on both the client and server sides Adapting to details of the new NA62 LTU firmware will be done in a short time after the firmware is ready New stuff: SIM proxies to provide interface to RUNCONTROL and/or DCS 15/12/201013

14. VME processorVME driverLTU DIM/SMI proxy DIM clients SMI GUI LTU DIM/SMI architecture DIM/SMI proxy Ob SMI DOMAIN "SMI_LTU" Obj CEDAR VETO STRAW TCP/IP 15/12/201014

15. 15/12/201015

16. What we presented here is a proof of concept. Details concerning SMI objects and actions are to be discussed with RUNCONTROL programmers. We are able to provide SMI proxies to be connected to (maybe third party) SMI managers We are ready if it is decided that RUNCONTROL and/or DCS would be based on SMI 15/12/201016 Summary concerning SMI

17. Summary We have asked to produce next 2 LTU boards in order to check quality of production If there will be any faulty component we will send the board back to company for replacement Basic firmware and software for testing of components on the LTU is ready Final firmware written in Verilog, partially done, simulation in CADENECE set-up. 15/12/201017