1. CSC Endcap Muon Sorter Mezzanine Board Rice University July 4, 2014

2. XC5VLX 110T- FF1136 12-ch Optical Transmitter Upgraded mezzanine board 12-ch Optical Receiver Virtex-2 XC2V4000 Mezzanine Board (initial version of the SP04) ■ Both mezzanines support 4 copper links to GMT ■ New mezzanine with 12-channel Avago AFBR-810 optical transmitter and 12-channel Avago AFBR-820 optical receiver 1

3. Why relatively old Virtex-5 FPGA? ■ Fully compatible with the 3.3V logic levels on the baseboard. Newer Xilinx families are only partially compatible (at best), but still can’t support 600+ 3.3V inputs/outputs. Adding of several dozens voltage translators between the FPGA and 6 mezzanine connectors is not feasible. ■ Have two devices in hand already. What do we have with the XC5VLX110T-FF1136C FPGA? ■ 640 general purpose i/o (marginal, but sufficient for the baseboard) ■ 16 GTP transceivers, up to 3.75Gbps data rate How can we use the new mezzanine? ■ Transmit 4 selected muons from the old CSCTF to the old GMT via four parallel copper links at 40Mhz (present scheme) ■ Transmit 4 selected muons from the old CSCTF to the new GMT/GT via 3.2Gbps optical links ■ Receive muons from the new CSCTF via optical receiver, transmit 4 “best” ones via parallel copper links to the old GMT 2

4. Status as of July 4, 2014 (1) ■ 6 boards have been fabricated, 2 of them assembled 3 12-channel optical transmitter 12-channel optical receiver

5. Status as of July 4, 2014 (2) ■ Bottom View 4

6. Status as of July 4, 2014 (3) ■ New mezzanine installed on the main Muon Sorter board 5

7. Status as of July 4, 2014 (4) ■ Initial test: - power (6 sources) OK - access to FPGA and PROM via Xilinx JTAG cable OK - VME access OK - Initial test with 12 Muon Tester boards (to replicate SP05) OK 6