1. Chuck Benz ASIC & FPGA Design csrGen: Automated CSRs for ASIC/FPGA Processor Interfaces Chuck Benz Chuck Benz ASIC & FPGA Design http://asics.chuckbenz.com

2. 2 Chuck Benz ASIC & FPGA Design 1 Outline Describe processor interfaces and CSRs Discuss automating CSRs Example using csrGen – template file and result More complete list of csrGen features Future directions

3. 3 Chuck Benz ASIC & FPGA Design 1 Example CSR memory map And so forth… And more4 More3 bitX6bitX5bitX4bitX3bitX2 bitX1 2 Field21 bitDbitCbitBbitAField10

4. 4 Chuck Benz ASIC & FPGA Design 1 Example CSR logic read data read mux write data write and address decode CS_L WR_L Address Interface logic

5. 5 Chuck Benz ASIC & FPGA Design 1 CSR verilog code fragments output [7:0] field2 ; reg [7:0] field2, field2_D ; always @ (*) begin field2_D = field2 ; if (write) case (address) 1: field2_D = up_datain[7:0] ; endcase case (address) 1: up_dataout_D[7:0] = field2 ; endcase always @ (posedge clock or negedge resetl) if ( ! resetl) field2 <= 0 ; else field2 <= field2_D ;

6. 6 Chuck Benz ASIC & FPGA Design 1 Why Automate? Time savings Correctness Consistency, shared structures Generate more than RTL code

7. 7 Chuck Benz ASIC & FPGA Design 1 Ways to Automate CSRs (1) Code fragments vs. complete RTL – create the fragments, maybe use `ifdef, OR – blend automated stuff with the rest of the Verilog code Results: – verilog (or VHDL?) RTL code – defines for verification, software code – declarations/instantiation for hierarchy – documentation (format?)

8. 8 Chuck Benz ASIC & FPGA Design 1 Ways to Automate CSRs (2) What types of CSRs ? – R/W – RO – sticky (COR/W1C) – counters (COR/W1C) – pulse Single or many modules Input format ?

9. 9 Chuck Benz ASIC & FPGA Design 1 csrGen example template part 1 %I read %I write %I address 4 %I up_datain 8 %OF up_dataout 8 %A 0 7:0 field1 %A 1 7:0 version RO %A 2 3:0 field2 6 someerror sticky W1C

10. 10 Chuck Benz ASIC & FPGA Design 1 csrGen example template part 2 %VCL if (write) case (address) %writecase endcase if (read) case (address) %readcase endcase %E %AUTO

11. 11 Chuck Benz ASIC & FPGA Design 1 csrGen example result part 1 module chip_up_ifc (/*AUTOARG*/) ; input clock, initl ; input [7:0] version; input someerror; input read; input write; input [3:0] address; input [7:0] up_datain; output [7:0] field1; output [3:0] field2; output [7:0] up_dataout; reg [7:0] field1, field1_D; reg [3:0] field2, field2_D; reg someerrorS, someerrorS_D; reg [7:0] up_dataout, up_dataout_D ;

12. 12 Chuck Benz ASIC & FPGA Design 1 csrGen example result part 2 always @ (/*AUTOSENSE*/) begin field1_D = field1 ; field2_D = field2 ; someerrorS_D = someerrorS | someerror ; up_dataout_D = up_dataout ;

13. 13 Chuck Benz ASIC & FPGA Design 1 csrGen example result part 3 Continuing the always block: if (write) case (address) 0: begin field1_D = up_datain[7:0] ; end 1: begin end 2: begin field2_D = up_datain[3:0] ; someerrorS_D = (someerrorS_D & ~up_datain[6]) | someerror ; end endcase

14. 14 Chuck Benz ASIC & FPGA Design 1 csrGen example result part 4 Finishing the always block: if (read) case (address) 0: begin up_dataout_D[7:0] = field1 ; end 1: begin up_dataout_D[7:0] = version ; end 2: begin up_dataout_D[3:0] = field2 ; up_dataout_D[6] = someerrorS ; end endcase end

15. 15 Chuck Benz ASIC & FPGA Design 1 csrGen example result part 5 always @ (posedge clock or negedge initl) if ( ! initl) begin field1 <= 0 ; field2 <= 0 ; someerror <= 0 ; up_dataout <= 0 ; end else begin field1 <= field1_D ; field2 <= field2_D ; someerrorS <= someerrorS_D ; up_dataout <= up_dataout_D ; end endmodule

16. 16 Chuck Benz ASIC & FPGA Design 1 Beyond simple Example is just basic, csrGen has many more features various CSR structures (more later) An address definition can be repeated – incrementing index appended to field names – or for single bits, constructing a vector spanning addresses %VCL and %V have simple repeat structure – the missing verilog Generate statement – simply unrolls a print statement ▪▪▪► any structure

17. 17 Chuck Benz ASIC & FPGA Design 1 More features Verilog tasks can be called for write or read to address Wide fields can be broken across several addresses Read multiplexer can be pipelined Reset value of flops can be set Direct value for flops bypasses _D structure

18. 18 Chuck Benz ASIC & FPGA Design 1 Supported CSR properties internal to module (no IO declarations for CSR field) read only write only sticky clear-on-read write-1-to-clear counters pulses (see paper on CD for full feature list, details)

19. 19 Chuck Benz ASIC & FPGA Design 1 Verification Automated definitions: – define csr_address_name 42 – define csr_width_name 8 – define csr_range_name 7:0 Allows for automated testing – R/W – reset values – clear on read, write-1-to-clear tests

20. 20 Chuck Benz ASIC & FPGA Design 1 Futures, Enhancements Open source tool, change as desired More CSR structures (send requests, enhancements) Generate HTML table for each address Parser and data structures could be better

21. 21 Chuck Benz ASIC & FPGA Design 1 Lessons, Ideas More than a tool – a concept of how design work can evolve “Spec driven design” – but small step rather than giant leap – focused on one area of a design – emphasis on integrating Other ways to do this – template file could be generated from other tool – emacs mode auto expansion from comments (pragmas) – object oriented design language ?

22. 22 Chuck Benz ASIC & FPGA Design 1 Conclusion Avoid tedious, error prone work Here's a tool for your tool box feedback is welcome csrGen.pl http://asics.chuckbenz.com cbenz@chuckbenz.com