1. Pattern Sensitive Placement For Manufacturability Shiyan Hu, Jiang Hu Department of Electrical and Computer Engineering Texas A&M University College Station, TX, 77843

2. 2 Outline Lithography system Lithography system Motivation Motivation Problem formulation Problem formulation Algorithms Algorithms Experimental results Experimental results Conclusion Conclusion

3. 3 Chip Design and Fabrication Lithography Process Designed Chip Layout Fabricated Chip

4. 4 Lithography Process oxidation optical mask process step photoresist coatingphotoresist removal (ashing) spin, rinse, dry acid etch photoresist stepper exposure development Typical operations in a single photolithographic cycle (from [Fullman]). Part of layout

5. 5 Lithography System Illumination Source Mask Objective Lens Wafer 193nm wavelength 45nm features

6. 6 Mask v.s. Printing 0.25µ0.18µ 0.13µ 90-nm65-nm Layout What you design is NOT what you get!

7. 7 Motivation Chip design cannot be fabricated Chip design cannot be fabricated –Gap Lithography technology: 193nm wavelength Lithography technology: 193nm wavelength VLSI technology: 45nm features VLSI technology: 45nm features –Lithography induced variations Impact on timing and power Impact on timing and power –Even for 180nm technology, variations up to 20x in leakage power and 30% in frequency were reported. Technology node 130nm90nm65nm45nm Gate length (nm) Tolerable variation (nm) 905.3533.7535 2.528 2 Wavelength (nm) 248193193193

8. 8 Gap: Lithography Tech. v.s. VLSI Tech. 193nm 28nm, tolerable distortion: 2nm Increasing gap  Printability problem more severe!

9. 9 Improve Printability by RET Resolution Enhancement Technique (RET) Resolution Enhancement Technique (RET) –Post Physical Layout Design –Weakness: Limited capacity and increasingly difficult Limited capacity and increasingly difficult Expensive mask cost Expensive mask cost OPC

10. 10 Design For Manufacturability (DFM) Efforts are needed in all design and process stages. Efforts are needed in all design and process stages. Physical design considering printability: Design For Manufacturability (DFM). Physical design considering printability: Design For Manufacturability (DFM). –To make RET easier and cheaper to apply

11. 11 Design For Manufacturability (DFM) Design people need to make the design easy to be printed Design people need to make the design easy to be printed Physical design considering printability: Design For Manufacturability (DFM). Physical design considering printability: Design For Manufacturability (DFM). –RET can be applied later for further improvement Maskwriter Physical Design Considering Manufacturability EDA TOOLS & FLOW Lithography Process RET TOOLS & FLOW Design IP Design IP

12. 12 Previous Works on DFM Regular fabric: Regular fabric: –Introduce regular geometry, similar to FPGA –Compromised performance Restricted design rules: Restricted design rules: –Not able to accurately capture lithography effects –Rule explosion: 2000 pages in 22nm technology (From DAC’05)

13. Previous Works on DFM Regular fabric: Regular fabric: –Introduce regular geometry, similar to FPGA –Compromised performance Restricted design rules: Restricted design rules: –Not able to accurately capture lithography effects –Rule explosion: 2000 pages in 22nm technology RET-friendly detailed placement (ASPDAC’05): RET-friendly detailed placement (ASPDAC’05): –Small spacing perturbation –No cell flipping, no cell relocation

14. 14 Our Problem Physical layout design considering manufacturability Physical layout design considering manufacturability Cell Placement Cell Placement –Given a circuit, decide the physical location of each gate –A major step in the physical layout design flow –Objectives: small wirelength, small area, good timing, etc. Placement

15. 15 This Work Post-placement optimization for printability Post-placement optimization for printability –Post-placement optimization Applicable to any existing placement to make it easier to print Applicable to any existing placement to make it easier to print Limit modification to retain benefits Limit modification to retain benefits –Improve printability Measurement of printability Measurement of printability How? How? –Relocation and Flipping

16. 16 Measurement of Printability Manufacturability cost Manufacturability cost –Edge Placement Error (EPE), Image Log Slope (ILS), process window,… : EPE From http://www.vlsitechnology.org/

17. 17 Our Optimization Existing Placer Relocation and Flipping Hard to print by simulation Easy to print by simulation

18. 18 Cell Flipping to Improve Printability 50% reduction in gate length deviation From http://www.vlsitechnology.org/

19. 19 Our Approach Offline: Offline: –For each possible pattern formed by two cells, assign a manufacturability cost Accurate lithography simulations Accurate lithography simulations Results saved in a lookup table Results saved in a lookup table Online: Online: –Prefer easy-to-print patterns in design horizontally adjacent cell pair Pattern: part between horizontally adjacent cell pair From http://www.vlsitechnology.org/

20. 20 Problem Formulation Given a cell placement Given a cell placement Perform post-processing optimizations, which can be cell flipping and relocation Perform post-processing optimizations, which can be cell flipping and relocation Total manufacturability cost (sum of manufacturability cost over all patterns) is reduced subject to the modification (wire length) constraint. Total manufacturability cost (sum of manufacturability cost over all patterns) is reduced subject to the modification (wire length) constraint.

21. 21 Optimization Considering Cell Flipping The algorithm is for row-based layout. The algorithm is for row-based layout. Perform optimization row by row. Perform optimization row by row. For each row of cells, perform the dynamic programming style optimization. For each row of cells, perform the dynamic programming style optimization.

22. 22 Optimizing A Row by Cell Flipping 1 2 After processing the last cell, pick the solution with best manufacturability cost while satisfying wirelength constraint

23. 23 Solution Characterization and Update Each candidate solution is associated with Each candidate solution is associated with –c: a cell –CE: cumulative manufacturability cost –CW: cumulative wire length c is being processed, c is being processed, –CE  CE + manufacturability cost of new pattern –CW  HPWL on all nets not spanning on any unprocessed cell. c

24. 24 Solution Pruning Two candidate solutions Two candidate solutions –Solution 1: (c, CE1, CW1) –Solution 2: (c, CE2, CW2) Solution 1 is inferior if Solution 1 is inferior if –CE1 > CE2 : larger cumulative manufacturability cost –and CW1 > CW2 : larger cumulative wirelength Whenever a solution becomes inferior, it is pruned. Whenever a solution becomes inferior, it is pruned.

25. 25 Single Row Optimization Allow both cell flipping and cell relocation. Allow both cell flipping and cell relocation. Partition a row of cells into groups. Partition a row of cells into groups. Small modification  a cell movable only within a group. Small modification  a cell movable only within a group.

26. 26 Flow for Single Row Optimization Partition a row of cells into groups Pick groups for optimization Perform group optimization tentatively Accept the result if printability is improved and overhead satisfies constraint Difficult

27. 27 Group Optimization Compute the placement with best manufacturability cost (no wirelength constraint) Compute the placement with best wirelength (initial placement) Tradeoff: gradually tune best manufacturability placement towards the best wirelength placement Difficult

28. 28 Placement with Best Manufacturability Cost : 0 : manufacturability cost

29. 29 Placement with Best Manufacturability Cost : 0 : manufacturability cost

30. 30 Placement with Best Manufacturability Cost : 0 : manufacturability cost

31. 31 Placement with Best Manufacturability Cost : 0 : manufacturability cost Flipped

32. 32 Placement with Best Manufacturability Cost : 0 : manufacturability cost

33. 33 Placement with Best Manufacturability Cost : 0 : manufacturability cost Every placement corresponds to a Hamiltonian path

34. 34 Minimum Cost Hamiltonian Path Problem The placement with best manufacturability cost  the minimum cost Hamiltonian Path The placement with best manufacturability cost  the minimum cost Hamiltonian Path –No wirelength constraint Well-known NP-hard problem Well-known NP-hard problem Closest point heuristic is used Closest point heuristic is used

35. Handle Wirelength Constraint Start from best manufacturability solution Gradually adjust it to satisfy wirelength constraint ABCDE BAEDC Best Manufacturability Best Wire Reduce crossings: fewer crossings  closer to best wire solution  possible to satisfy the wirelength constraint Reduce crossings: fewer crossings  closer to best wire solution  possible to satisfy the wirelength constraint

36. Handle Wirelength Constraint Start from best manufacturability solution Gradually adjust it to satisfy wirelength constraint ABCDE BAEDC Best Manufacturability Best Wire

37. Handle Wirelength Constraint Start from best manufacturability solution Gradually adjust it to satisfy wirelength constraint ABEDC BAEDC Best Wire Able to get the solution with good manufacturability cost satisfying the wirelength constraint Able to get the solution with good manufacturability cost satisfying the wirelength constraint

38. 38 Multiple Row Based Optimization Motivation Motivation –A net often spans adjacent rows –Moving cells in different rows simultaneously may reduce wirelength –Some previously “infeasible” manufacturability-driven placement may become “feasible”. More options. Feasible: satisfy wirelength constraint Feasible: satisfy wirelength constraint –Improved manufacturability cost

39. 39 Experiments Experiment Setup – –ISCAS’ 89 (>10K cells in a circuit) and ISPD’ 04 benchmark (>200K cells in a circuit) – –130nm technology – –SPLAT for lithography simulation – –1% wire length increase bound – –Lookup table size: <1M – –Lookup table access time: <0.1 ɥ s per entry – –A Pentium 4 machine with a 3.0GHz CPU 2G memory

40. 40 ISCAS’89: EPE reduction %

41. 41 ISCAS’89: Wirelength Increase %

42. 42 ISCAS’89: Runtime (seconds)

43. 43 Observations Cell Flipping: Cell Flipping: –9% EPE reduction –0.17% additional wire –Fastest Single Row Optimization: Single Row Optimization: –14.6% EPE reduction –0.35% additional wire –2x slower compared to Cell Flipping Multiple Row Optimization Multiple Row Optimization –22% EPE reduction –0.57% additional wire –4x slower compared to Cell Flipping

44. 44 ISPD’04: EPE Reduction %

45. 45 ISPD’04: Wirelength Increase % Percentage

46. 46 ISPD’04: CPU (s)

47. 47 Observations Cell Flipping: Cell Flipping: –11% EPE reduction –0.16% additional wire –Very fast Single Row Optimization: Single Row Optimization: –18% EPE reduction –0.29% additional wire –50% slower Multiple Row Optimization: Multiple Row Optimization: –25% EPE reduction –0.41% additional wire –2x slower

48. 48 Conclusion Propose three algorithms for pattern sensitive placement for manufacturability: – –Cell Flipping only – –Single Row Optimization – –Multiple Row Optimization >20% edge placement error reduction. <1% wire length overhead. Runtime acceptable for large placement benchmark.

49. 49