© 2000 Altera Corporation 1 Designing with Quartus.

© 2000 Altera Corporation 2 Class Goals Learn more about the capabilities in Quartus Learn to use different design entry techniques –Design entry methods available within Quartus Text editor Block diagram/schematic file editor –Quartus interface with design entry/synthesis tools from Exemplar, Synopsys, Synplicity and Viewlogic

© 2000 Altera Corporation 3 Class Goals Learn about verification using other EDA tools –Interfacing with simulators and timing analyzers from Cadence, Model Technology, Synopsys, and Viewlogic Learn to use timing analysis Learn how to make timing assignments Learn to use the Quartus simulator Learn about scripting in Quartus

© 2000 Altera Corporation 5 Introduction to Altera An industry leader in programmable logic –Inventor of the EPLD in 1983 Eight programmable logic families –Look-up table-based and product term-based APEX 20K –Look-up table-based FLEX 6000, FLEX 8000, FLEX 10K –Product term-based Classic, MAX 3000, MAX 7000, MAX 9000 Software development systems: Quartus, MAX+PLUS II

© 2000 Altera Corporation Quartus Development System Quartus Development System features: –Fully integrated design entry, processing, and verification tools: Multiple design entry methods Logic synthesis Place & route Simulation Timing analysis Device programming –NativeLink –Revision Control Interface –Intellectual Property (IP) Support –SignalTap –Extensive On-Line Help

© 2000 Altera Corporation 8 More Features Incremental Recompilation Internet-enabled technical support Supports multiple platforms 1 –Quartus runs on Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations Extensive on-line help Network licensing supported on both Windows-based PCs and Unix-based workstations Note 1: Please refer to Quartus’ ReadMe file to determine which version of the Operating System is supported for each platform

© 2000 Altera Corporation 10 System Production Design Specification Design Compilation Functional Verification Timing Verification Device Programming In-System Verification Design Modification Design Entry Command-Line Mode: Scripting

© 2000 Altera Corporation 11 Design Entry Multiple design entry methods –Quartus Block/Schematic Editor Text Editor –AHDL, VHDL, Verilog Memory Editor –Hex, Mif –Third party EDA tools EDIF HDL VQM –Add flexibility and optimization to the design entry process by: Mixing and matching design files Using LPM and Megafunctions to accelerate design entry

© 2000 Altera Corporation 12 Quartus Memory Editor Quartus Text Editor Quartus Block Editor Top- Level File.bdf.gdf Top-level design files can be.bdf,.tdf,.vhd,.vhdl,.v,.vlg,.edif or.edf.bsf.vhd Block File Symbol File Text File Text File.v Text File Imported from third- party EDA tools Exemplar, Synopsys, Synplicity, etc... Generated within Quartus VHDL Schematic.tdf Text File AHDLVerilog.edf.edif Text File.v,.vlg,.vhd,.vhdl, vqm MegaWizard Manager Design Entry Files

© 2000 Altera Corporation 13 Text Design Entry Available Features –Line numbering in the HDL text files –Preview of HDL templates –Syntax Coloring –When editing a text file, an asterisk (*) appears next to the filename After saving the file, the asterisk disappears Enter text description –AHDL (.tdf) –VHDL (.vhd) –Verilog (.v)

© 2000 Altera Corporation 14 AHDL Altera Hardware Description Language High-level hardware behavior description language Uses Boolean equations, arithmetic operators, truth tables, conditional statements, etc. Can create AHDL Design File (.tdf) with the Quartus text editor or any standard text editor and compile it directly with Quartus Text editor has AHDL templates and syntax coloring

© 2000 Altera Corporation 15 Learn more about Verilog in Altera Verilog Customer Training Classes Verilog 1993 Verilog IEEE 1364 standard Hardware Description Language Can create Verilog design files with the Quartus text editor or any standard text editor and compile it directly with Quartus Text editor has Verilog templates and syntax coloring Features –Tasks –2-D Arrays –Empty placeholder –State machine recognition –Verilog TestBench support

© 2000 Altera Corporation 16 Learn more about VHDL in Altera VHDL Customer Training Classes VHDL VHSIC Hardware Description Language 1987 and 1993 IEEE 1074 standards supported Can create VHDL design files (.vhd) with the Quartus text editor or any standard text editor and compile it directly with Quartus Text editor has VHDL Templates and syntax coloring VHDL TestBench support

© 2000 Altera Corporation 17 Block Diagram/Schematic File Editor This is both a block diagram editor and a schematic file editor Block diagram entry is mainly for top-down design methodology Schematic file entry is the traditional schematic design entry User can enter blocks, primitives, LPMs, and megafunctions from Quartus-provided or user libraries Provides “smart” block connection and mapping

© 2000 Altera Corporation 18 Block Editor - Entry Process Create new block design file –Draw block diagram or enter design components (symbols) –Enter port and parameter information –Connect components with connectors (wires, buses & conduits) –Add mapping properties to conduits, if needed Save the design –The file extension is.bdf Generate HDL/graphic file for the lower-level blocks Create symbol or include file of the top-level block design

© 2000 Altera Corporation 20 Block Editor - Enter Symbols Symbol libraries Click on the toolbar option “Insert Symbol” OR Double-click in block editor to insert symbols Preview the Symbol Enter symbols from libraries - LPMs, primitives, others

© 2000 Altera Corporation 21 Right-click on the block. Select Properties from the pop-up menu. Enter port information. Click on the toolbar option “Block” to draw a block diagram Block Editor - Draw Block Create block using the toolbar and enter ports Block A

© 2000 Altera Corporation 24 MapperConnector Block Editor - “Smart” Connections Quartus has “smart” block connecting and mapping –Unnecessary to label conduits if the I/O names between different blocks are the same –One conduit will connect all the common I/Os between the blocks Block ABlock B

© 2000 Altera Corporation 25 Block Editor - Conduit Properties Map the block I/Os when the I/O names are different between the blocks 1 First, label the connector Select connector  right-click  choose Properties  enter Name Block B ConnectorAB Enter Signal Block A

© 2000 Altera Corporation 26 Double-click on the mapper ConnectorAB Block B Mapper Properties 2 Select the mapper and double-click on it to open the Mapper Properties dialog box 3 In the General tab, set the Mapper Type - Input, Output, Bidir 4 In the Mappings tab, set the I/O on block and connector signal 5 Click Add and hit OK Block A

© 2000 Altera Corporation 29 Block Editor - Generate Design File Create HDL or graphic design file for individual blocks Right-click on the symbol to open the pop-up menu Select Create Design File from the menu Block A ConnectorAB Block B

© 2000 Altera Corporation 31 Create Design File module myblk ( // {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE! in1, in2, out1, out2 // {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE! ); // Port Declaration // {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! input in1; input in2; output out1; output out2; // {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! endmodule These lines are necessary for Quartus to update the source code Quartus creates a design file that contains the port names that are specified in your block.

© 2000 Altera Corporation 32 Update Design File... Right mouse click Update Design File... If you change the name or number of I/Os in your block, Quartus can update the design file for you Before After

© 2000 Altera Corporation 33 Updated Design File module myblk ( // {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE! in1, in2, out1, out2, out3 // {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE! ); // Port Declaration // {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! input in1; input in2; output out1; output out2; output out3; // {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! endmodule Quartus updated the source file with the additional pin, out3

© 2000 Altera Corporation 34 Menu Bar: Tools > Create Symbol for Current File Menu Bar: Tools > Create Include File for Current File Block Editor - Designing Hierarchically? Creates.bsf file Creates.inc file

© 2000 Altera Corporation 36 Memory Editor Create or edit memory files in hex format (.hex) or memory initialization format (.mif) For Design Entry –If you have a memory block in your design (ex. RAM, ROM, or Dual-port RAM), you can use the memory editor to create a memory initialization file to initialize your memory block For Simulation –You can create an initialization file to initialize your memory during simulation

© 2000 Altera Corporation 42 Memory Editor - Edit Contents Create memory file –Edit contents of the memory file Select the word and type in a value OR Select the word and right click to select an option from the pop-up menu

© 2000 Altera Corporation 44 Need to Edit Memory Size Contents? Quartus Provides the Memory Size Wizard –Edit Word Size –Edit Number of Words –Specify How to Handle Word Size Change Increasing Word Size –Pad Words –Combine Words Decreasing Word Size –Truncate Words From Left –Truncate Words From Right. Memory Editor - Memory Size Wizard

© 2000 Altera Corporation 46 Memory Editor - Memory Size Wizard Decreasing Memory Size 3a. How should Quartus handle excess bits? - Truncate MSBs - Truncate LSBs - Split Words/Increase Memory Depth 16 bits 8 bits To

© 2000 Altera Corporation 47 Memory Editor - Memory Size Wizard Increasing Memory Size 16 bits 32 bits 3b. How should Quartus pad words? - Combine Words - Sign Extend (Signed) - Pad MSBs With Zeros (Unsigned) To

© 2000 Altera Corporation 49 Quartus NativeLink interface is comprised of two components: –External Files: WYSIWYG (What You See Is What You Get) ATOM netlist files (EDIF, Verilog, VHDL) cross reference files (ex. xrf), timing files (ex. sdo) etc. –Application Programming Interface (API) Functions - a pre- defined interface EDA Partners API External Files NativeLink Quartus

© 2000 Altera Corporation 50 NativeLink Features Minimizes designer interaction with different EDA tools –Allows designers to complete their designs using as little as one tool Cross-referencing –Nodes from place-and-route result can be traced back to HDL code across from Quartus to a synthesis tool Improved Quality of Results (QoR) –Nativelink lets synthesis tools map directly into the fundamental building block of an architecture Iterative Compile –Improves QoR from synthesis tools –Allows Quartus to pass routing delay information after place-and- route back to the synthesis tools –Synthesis tools can then re-synthesize the design based on the feedback

© 2000 Altera Corporation 51 Quartus Driven Flow –EDA tools launched from within Quartus –Code level integration Cross probing and error location –Quartus automatically generates the netlists or reads in the netlists based on the tool –User doesn’t have to learn the setup and the flow Synthesis Tool Tcl COM (C++, VBScript) API Cross Probe Error Locate Quartus drives the third party EDA software

© 2000 Altera Corporation 52 Vendor Driven Flow –Offers the tightest code-level integration between tools –Quartus appears ‘Native’ in third party EDA software Third party EDA software drives Quartus Synthesis Tool Tcl COM (C++, VBScript) Cross Probe Error Locate API

© 2000 Altera Corporation 53 Synthesis Tools Design Compiler FPGA Express FPGA Compiler FPGA Compiler II Altera Edition General Version Leonardo Spectrum Synplify Simulation Tools ModelSim Verilog-XL Timing Analyzers: Motive Primetime Tools Supported by NativeLink 1 1 1 Note 1: These synthesis tools generate WYSIWYG ATOM netlists and support iterative compile capability

© 2000 Altera Corporation 56 Project Definition Quartus project: –A collection of related design files and libraries –Must have at least one designated top level entity –Targets a single device or can be partitioned into multiple devices –Stores project settings in Project Settings File (.PSF)

© 2000 Altera Corporation 57 Project Summary Use Project Wizard to create new projects Use Project Menu dialog boxes to –Edit existing project settings Add/Remove Files and/or Libraries –Set up Third Party interface Use Project Navigator to study file and entity relationships within the project See Appendix “Quartus Projects” for Further Information

© 2000 Altera Corporation 59 What are Compiler Settings? Compiler control information –Device assignment –Pin assignments –Level of compilation –Focus point of compilation in hierarchy –Synthesis & fitting –Verification Accessed via the Processing Menu Each contains a focus point Information stored in a Compiler Settings File (.CSF)

© 2000 Altera Corporation 60 Compilation Summary Use Compiler Wizard to create new Compiler Settings Use Compiler Settings dialog boxes to change existing compiler settings & make pin assignments Use Compiler Report to study design implementation and resource usage Use Assignment Organizer to assign logic options See Appendix “Quartus Compilation” for Further Information

© 2000 Altera Corporation 63 Features Quartus is capable of doing single clock design timing analysis and multi-clock design timing analysis Single clock timing analysis –Fmax (maximum clocking frequency) –Tsu, Th, Tco (setup time, hold time, clock-to-out time) –Slack analysis for Fmax (incl. delays to/from pins) Multi-clock analysis –Allows user to analyze timing for a design containing register-to- register paths which are controlled by different clocks –Slack analysis is used Combinatorial Loop Detection –Quartus automatically detects combinatorial loops

© 2000 Altera Corporation 64 Features Different types of timing information (Refer to the compilation section for more information) –Timing without place & route –Timing with place & route –A mix of both for a hierarchical design By default, timing analysis is performed automatically after compilation –Can be disabled Timing information can be exported to other EDA tools via VHDL, Verilog and Standard Delay File (SDF)

© 2000 Altera Corporation 65 In This Section Timing analysis for a single clock system –Register Performance –Setup Time –Hold Time –Clock-to-Out Making Timing Assignments Timing analysis of a multi-clock system How to make multi-cycle assignments Timing Wizard

© 2000 Altera Corporation 66 Compile Design Step 2: Investigate the type of delay in this design Step 1: The internal fmax is 83.19 Mhz. This value is automatically given for each clock in the Message Window (Processing Tab)

© 2000 Altera Corporation 67 Timing information is part of the Compilation Report –Summary Timing Analyses –fmax (not incl. delays to/from pins) or fmax (incl. delays to/from pins) –Register-to-Register Table –tsu (Input Setup Times) –th (Input Hold Times) –tco (Clock to Out Delays) –tpd (Pin to Pin Delays) All timing results are reported here Reporting Timing Results

© 2000 Altera Corporation 68 fmax (not incl. delays to/from pins) Clock Period = Clock-to-out + Data Delay + Setup Time - Clock Skew = tco + B + tsu - (E - C) Fmax = 1/Clock Period B C tcotsu E Clock Period

© 2000 Altera Corporation 70 fmax Analysis Expand to see the source registers feeding the selected destination register Source registers and associated fmax values Timing Analysis By Default Lists 10 Worst Paths – Can Change in Project -> Timing Settings (discussed later)

© 2000 Altera Corporation 72 fmax Analysis Data Delay (B) Source Register Clock Delay (C) Setup Time (tsu) B C tcotsu E Clock Period Destination Register Clock Delay (E) Clock to Output (tco) 1 0.33 ns + 11.257 ns + 0.45 ns + 0.00 = 83.08 MHz Messages Window (System Tab) in Quartus

© 2000 Altera Corporation 73 fmax Analysis Interconnect Delay Cell DelayRunning Total The convention above is similar for all timing path analysis in Quartus This signal path consists of 11 locations Destination Cell

© 2000 Altera Corporation 74 0.000 ns + 0.191 ns = 0.191 ns 0.000 ns is the carry chain delay (interconnect delay) 0.191 ns is the combinatorial delay Note: If the delay path involves a carry chain, you can only see the delay path value in the Floorplan when the Floorplan is set to Logic Cell View. LAB View does not show that delay path. 0.191ns is equal to the carry chain delay plus combinatorial delay Floorplan: Logic Cell View Carry Chain in Data Delay Path

© 2000 Altera Corporation 77 Fmax (incl. delays to/from pins) System Fmax = 1 / (the longest of the 3 following delays: Clock Period, Input Pin Period, Output Pin Period) Clock Period = C + tco + B - E + tsu Input Pin Period = External Input Delay + A - C + tsu Output Pin Period= E + tco + Q + External Output Delay A C tcotsu E External Input Delay External Output Delay Clock PeriodInput Pin PeriodOut Pin Period B Q

© 2000 Altera Corporation 79 External Input Delay External Input Delay is used to model the delay between an imaginary register and a register inside an Altera device External Input Delay = EC + tco + ET Input Pin Period = External Input Delay + A - C + tsu EC ETA C tcotsu Altera DeviceExternal Input Delay Imaginary Register

© 2000 Altera Corporation 81 External Output Delay External Output Delay is used to model the delay between a registered output from an Altera device to an imaginary register External Output Delay = ET + tsu - EC Output Pin Period = E + tco + Q + External Output Delay E QET tco dst External Output DelayAltera Device EC Imaginary Register tsu

© 2000 Altera Corporation 82 Fmax (incl. delays to/from pins) Select fmax (incl. Delays to/from pins) Fmax values The worst fmax is shown at the top by default. External Delay is shown in Messages Window after List Path

© 2000 Altera Corporation 84 Setting External Input/Output Delay Individual Pin(s) 1) Tools -> Assignment Organizer 2) Locate Pin(s) 3) Select Timing from Assignment Categories 3) Set Delay Value(s) for Pin(s)

© 2000 Altera Corporation 91 Used to Limit Which Paths Are Displayed by Timing Analyzer Two Ways to Set Options –Project -> Timing Settings -> Other Requirements & Options –Project -> Timing Wizard Examples –Cut Off Feedback From I/O Pins (next slide) –Cut Off Clear and Preset Signal Paths If checked, Quartus Will Not Analyze Register Clear and Preset Delays –Cut Off Read During Write Signal Paths Turn ON if Read During Write is an Invalid Path Timing Analysis Options

© 2000 Altera Corporation 92 Option: Cut Off Feedback from I/O Pin clk QD A Register 1 Register 2 Global Timing Option: Cut off feedback from I/O Pin Used to break I/O pin from the analysis When on, paths A and B are valid. C is not valid. When off, paths A, B, and C are valid. I/O Pin C B

© 2000 Altera Corporation 94 Used to Limit How Many Paths Are Displayed by Timing Analyzer How to Set Option –Project -> Timing Settings -> Timing Analysis Reporting Examples –Show “XX” Source Nodes Per Destination Node Controls by Number How Many Paths Are Displayed –Exclude Paths With fmax Greater Than “XX” Controls by Parameter Value (fmax) How Many Paths Are Displayed –Exclude Paths For tsu, tco, thd Also Timing Analysis Options

© 2000 Altera Corporation 96 Single Clock Timing Analysis The timing analysis that we just went over can be classified as a single clock frequency analysis Single clock frequency analysis is automatically done during each compile Quartus will automatically detect clocks if no assignments are made –More information about clock assignments is coming up in multi- clock timing analysis Check results in Report Window

© 2000 Altera Corporation 98 Timing Assignments Timing assignments have two impacts on designs –1. During timing analysis, they specify required times the design is measured against –2. During compilation, they become timing requirements which Quartus has to meet when performing timing driven compilation (TDC) Note: by default, TDC is on 5 types of timing assignments exist: –fmax, tsu, thold, tco, tpd These timing assignments can be assigned globally or locally

© 2000 Altera Corporation 99 Examples of Timing Assignments fmax timing assignment The values are BLACK, because Actual fmax meets the Required fmax tsu timing assignment. The numbers are RED, because the Actual tsu does not meet the Required tsu Timing Assignments used in Timing Analysis

© 2000 Altera Corporation 100 Timing Driven Compilation Timing Driven Compilation (TDC) directs the compiler to synthesize and place logic to meet timing specified requirements –Critical paths will be placed closer together in the device Optimize for I/O Timing and/or Internal Timing Choose Normal or Extra Effort (works harder & takes longer)

© 2000 Altera Corporation 101 Global Assignment: Timing Settings For a design with separate clocks, you can enter the required fmax. The Default required fmax will be applied to each individual clock in the design. Global Clock Assignment for a single clock design

© 2000 Altera Corporation 102 Global Assignments - Timing Settings Global tsu. All input or bidirectional pins are measured against this tsu requirement Global tpd. All pin-to-pin delays are measured against this tpd requirement Global tco. All registers driving outputs or bidirectional pins are measured against this tco requirement Global th. All input or bidirectional pins are measured against this th requirement

© 2000 Altera Corporation 103 Individual Assignments tsu (setup time) and th (hold time) assignments –Single point assignment –Point-to-point assignment tco (clock-to-out) assignment –Single point assignment –Point-to-point assignment

© 2000 Altera Corporation 105 Assign single point setup/hold requirement to the data pin Setup/Hold Requirements Assignments can be either single point or point-to-point Single point setup/hold requirements –States that the setup/hold time is required on every register that the pin feeds

© 2000 Altera Corporation 106 Assign point-to-point setup requirement to the input pin and the destination register Setup/Hold Requirement: Point-to-Point The setup/hold time is required only for the specified path Reg1 Reg2 data0

© 2000 Altera Corporation 107... Clock To Out Requirements Either a single point or a point-to-point assignment Same idea as setup/hold time requirements Tco requirement on a clock pin –Means that all Tco paths that start from the specified clock must meet this requirement

© 2000 Altera Corporation 110 Example: Assign Setup Requirement Step 2: Select Timing from the Assignment Category box Step 3: Choose tsu Requirement from the drop-down list in the Settings section Step 1: Enter the data pin name or use the Node Finder to locate data pin name and/or register name Menu Bar: Tools > Assignment Organizer...

© 2000 Altera Corporation 111 Example: Assign Setup Requirement Step 4: Type in the setup requirement Step 6: Click Add to add the assignment Step 5: Use Fed by: to create a point-to- point requirement

© 2000 Altera Corporation 112 Multi-Clock Frequency Analysis Allows user to analyze timing for a design containing register-to-register paths which are controlled by different clocks –Unless Specified, Quartus Treats Individual Clocks As Having the Same Frequency and Phase clk1 tco tsu Combinatorial logic clk2 capturing edge launching edge clk1 clk2 data Register 1 Register 2

© 2000 Altera Corporation 113 Slack Between Two Clock Domains Slack is used to keep track of the delay between Register 1 and Register 2 Positive Slack –If the slack is positive, then the data from Register 1 will meet the setup time of Register 2 Negative Slack –If the slack is negative, then the data from Register 1 will violate the setup time of Register 2 clk1 tco tsu Combinatorial logic clk2 data Register 1 Register 2

© 2000 Altera Corporation 114 Equation for Slack Slack = Required Time - Actual Time Slack = Slack Clock Period - ( Intrinsic tco + Data Delay + Intrinsic tsu ) launching edge clk1 clk2 capturing edge Slack clock period clk1 tco tsu Combinatorial logic clk2 data Register 1 Register 2 data delay

© 2000 Altera Corporation 115 Calculating Slack in Quartus In order for Quartus to calculate the Slack between registers, timing assignments need to be entered by the user IMPORTANT: The slack section inside the compilation report file does not appear automatically for a multi-clock design –Timing assignments need to take place first

© 2000 Altera Corporation 116 Slack Analysis: Steps to Follow Follow the steps below to prepare Quartus for Slack Analysis –Create Clock Settings Define a base clock Define other clock/s that is/are relative to the base clock –Assign Clock Settings to actual clocks –Recompile design –Look at result in the slack timing table

© 2000 Altera Corporation 117 Create Clock Settings Minimum of 2 clock settings exist for a multi-clock design: –One is a base clock –Second is a derived clock referenced to a “base” clock Derived clocks can be any ratio (m/d) of base clock plus an added offset, if desired. Note: If the design has more than 2 clocks, additional derived or base clocks can be created offset capturing edge launching edge base clock derived clock derived clock = base clock x (m/d) + offset

© 2000 Altera Corporation 119 Create Clock Setting: Base Clock Menu Bar: Project > Timing Settings... Step 2: Enter the name of the clock setting Step 3: Select Independent of other clock settings Step 4: Adjust fmax and Duty Cycle Step 5: Click OK to Add Setting

© 2000 Altera Corporation 121 Create Clock Setting: Derived Clock Menu Bar: Project > Timing Settings... Step 2: Enter the Name of the Derived Clock Setting Step 3: Select clock setting that this derived clock is based on Step 4: Click on Derived Clock Requirements

© 2000 Altera Corporation 122 Create Clock Setting: Derived Clock Step 5: Adjust ratio and offset. The derived clock duty cycle is not affected by the multiply base or the divide base. Invert base clock is also available. Click OK when done. Step 6: Click OK to Add Setting

© 2000 Altera Corporation 123 Current Clock Settings At this point, an absolute clock setting called base clock and a derived clock setting called derived clock have been created. The next step is to apply these clock settings to the actual clock nets. Absolute clock setting called base Derived clock setting called derived

© 2000 Altera Corporation 124 Slack Analysis: Steps to Follow Follow the steps below to prepare Quartus for Slack Analysis – Create Clock Settings Define a base clock Define other clock/s that is/are relative to the base clock –Assign Clock Settings to actual clocks –Recompile design –Look at slack results in compilation report file

© 2000 Altera Corporation 125 Assign Absolute Clock Settings to Clock Menu Bar: Tools > Assignment Organizer... Step 1: Enter the name of the clock pin. The naming convention is: | | of the pin> or click on the Node Finder to select the clock pin Step 2: Click on Timing and select Clock Setting Step 3: Select Base Clock Settings for this specific clock pin. Click on Add Derived Clock Setting: Repeat Step 1 to Step 3 for the derived clock setting

© 2000 Altera Corporation 126 Slack Analysis: Steps to Follow Follow the steps below to prepare Quartus for Slack Analysis – Create Clock Settings Define a base clock Define other clock/s that is/are relative to the base clock – Assign Clock Settings to actual clocks –Recompile design –Look at slack results in compilation report file

© 2000 Altera Corporation 128 Slack Distribution IMPORTANT: Negative Slack Time needs to be corrected in order for the design to work Select Determine if any and/or how many nodes receive a negative slack?

© 2000 Altera Corporation 129 Slack Time Table Slack Time Table offers more details about the source nodes and destination nodes –Positive slack means the timing was met –Negative slack shows by how much the timing was not met –IMPORTANT: Design needs to be altered or multi-cycle timing requirement/s is/are needed to resolve the negative slack issues Negative slack times show up in red and are listed at the top of the table Select

© 2000 Altera Corporation 130 Slack Analysis: Steps to Follow Follow the steps below to prepare Quartus for Slack Analysis – Create Clock Settings Define a base clock Define other clock/s that is/are relative to the base clock – Assign Clock Settings to actual clocks – Recompile design – Look at slack results in compilation report file

© 2000 Altera Corporation 131 Multicycle Paths Signal Paths That Intentionally Require More Than One Cycle to Become Stable –Must Be Considered in Design Implementation Declaring a Multicycle Path Tells the Timing Analyzer to Account for Multiple Clock Edges Between Nodes or Clock Domains launching edge base clock derived clock capturing edge

© 2000 Altera Corporation 132 Assigning Multicycle Paths Destination Register –Multi-cycle assignment is applied to all signal paths feeding register Register-to-Register –Point-to-point assignment that applies to one source register and one destination register Two Clock Domains –Assignment applies to all signals that travel from one clock domain to another launching edge base clock derived clock capturing edge

© 2000 Altera Corporation 133 Comparable Offset vs. Clock Period If the value of your offset is comparable to the value of the clock period, then a multi-cycle assignment on the derived clock is usually unnecessary. –ex. offset = 11ns, clock period = 20ns offset capturing edge launching edge base clock derived clock

© 2000 Altera Corporation 134 Relatively Small Offset vs. Clock Period If the offset value is relatively small compared to the clock period, then a multi-cycle assignment is usually necessary on the derived clock –Ex. Clock period = 10ns, offset = 2ns –The offset can be thought of as clock skew offset Intended capturing edge launching edge However, by default, Quartus assumes this is the capturing edge base clock derived clock

© 2000 Altera Corporation 135 launching edge true clock (base clock) complement clock (derived clock) capturing edge Inverted Clock If your design uses both the true and complement of the same clock signal, then a multi-cycle assignment is not necessary –You can assign the true clock as the base clock –You can assign the complement as the inverse of the base clock

© 2000 Altera Corporation 136 base clock (source) derived clock (destination) Non-Integer Multiples If the design clocks are non-integer multiples of each other, then a multi-cycle assignment may be necessary –Quartus analyzes two closest edges of base & derived clocks Ex. base clock = derived clock * 3/4 These two edges are most likely to cause a setup violation of the destination register

© 2000 Altera Corporation 137 base clock (source) derived clock (destination) Non-Integer Multiples If the design clocks are non-integer multiples of each other, then a multi-cycle assignment may be necessary –Quartus analyzes two closest edges of base & derived clocks launching edge capturing edge 12 Ex. base clock = derived clock * 3/4

© 2000 Altera Corporation 138 Multi-Cycle Assignment Multi-cycle assignment on the derived clock indicates the capturing edge is not the closest rising edge. offset capturing edge launching edge Multi-cycle assignment indicates this is the capturing edge base clock derived clock 1) For multi-cycle assignments, the capturing edge is the reference edge 2) The base clock is the reference clock for counting the number of edges between the capturing edge and launching edge 1 2

© 2000 Altera Corporation 139 Making a Multi-Cycle Assignment 1) Choose Timing and Multicycle from the Assignment List Menu Bar: Tools > Assignment Organizer... 2) Specify the number of edges 3) Use Fed by if creating two clock assignment or point-to-point

© 2000 Altera Corporation 140 Easy way to enter timing assignments Consolidates all timing assignments in one menu –Individual clock settings OR overall circuit frequency –Default system timing tsu th tco tpd –Default external input/output delays –Enable/Disable timing analysis during compilation –Timing driven compilation Timing Wizard

© 2000 Altera Corporation 142 Summary Timing analysis for a single clock system –Registered Performance –Setup Time –Hold Time –Clock-to-Out Making Timing Assignments Multi-clock timing analysis Multi-cycle timing assignments Timing Wizard

© 2000 Altera Corporation 144 In This Section Floorplan Editor Floorplan Editor Views –Compiled Floorplan view –Current assignments –Making assignments –MegaLAB, LAB, and LC views –Device top and bottom views Viewing Delays

© 2000 Altera Corporation Floorplan Editor Graphical user interface for creating/viewing resource assignments –Pins –Logic cells –Cliques Drag-and-drop capability for assigning pins/logic cells Graphical view of current assignments and compilation results MegaLAB, LAB, or Logic cell view

© 2000 Altera Corporation Assignments from Floorplan Editor Select Last Compilation and Current Assignments Floorplan views from processing menu Drag & Drop from Last Compilation View to Current Assignments View Last Compilation Floorplan View Current Assignments View

© 2000 Altera Corporation 152 Viewing Delays View delays between LCs Can locate and view delays of critical paths Delays annotated to Floorplan Delays Shortcut Shortcut to view Fan-in and Fan-out of LCs

© 2000 Altera Corporation 153 Summary Floorplan Editor is a graphical user interface for viewing/creating resource assignments Floorplan Editor has different views –Last compilation view –Current Assignments view –Top or bottom package view –LC, LAB, or MegaLAB view View Delays

© 2000 Altera Corporation 155 In This Section Simulator –Features –Supported simulation methods –3rd party simulators Simulator settings –Simulation Modes –End Time –Options –Simulation Focus –Saving Simulator Settings

© 2000 Altera Corporation 156 In This Section Continued Creating a Vector Waveform File (.VWF) –Customizing filter –Inserting nodes –Simulation length –Time bars –Creating signal patterns, clocks –Bidirectional pins Simulation –Simulator Report –Comparing waveforms

© 2000 Altera Corporation 158 Simulator supports 9 different signal values –1Forcing ‘1’ –0Forcing ‘0’ –XForcing unknown –UUninitialized –ZHigh impedance –HWeak ‘1’ –LWeak ‘0’ –WWeak unknown –DCDon’t Care Features

© 2000 Altera Corporation 159 Features Continued Bidirectional pins can be represented as a single signal Easy to use Node Finder –Can customize filter Multiple time bars –Master, relative, and absolute Simulator automatically –Adds output pins to output waveform file –Checks outputs at the end of simulation –Invokes compiler from simulator

© 2000 Altera Corporation 160 Supported Simulation Methods Waveform entry –.vwf (vector waveform file) - primary waveform file for Quartus –.vec (vector file) - MAX+PLUS II.vec file supported for backward compatibility –.tbl (table file) - used to import existing MAX+PLUS II.scf files into Quartus Testbench support –Tcl/TK scripting –Verilog/VHDL 3rd Party Simulators

© 2000 Altera Corporation 163 Saving Simulator Settings Simulator settings determine the type of simulation that is performed Quartus allows simulator settings to be saved Specify the simulator setting 2 Save simulator setting 1 Specify simulator setting on which to focus 3

© 2000 Altera Corporation 164 Simulator End Time Specifies the start time and end time of simulation Enter end time Enter start time Runs simulation to the end of the stimulus file Displays comparison of simulation in simulator report

© 2000 Altera Corporation 167 Simulator Options Reports ratio of simulated nodes to number of nodes in.vwf file Reports setup and hold time violations in message window Monitors simulation for glitches and reports them in message window Specify time interval that defines Glitch

© 2000 Altera Corporation 172 Customizing Filter in Node Finder Filter is used to search for nodes Creates new filter 2 Select netlist 3 Name of filter being customized Select type of node 4 Customize filter 1

© 2000 Altera Corporation 173 Selecting Nodes for Waveform File In Node Finder box enter nodes into Selected Nodes field Select node Enter node into Selected Nodes field Can select entire bus or single bit

© 2000 Altera Corporation 177 Creating a Clock Highlight waveform and enter period Clock shortcut 2 Highlight waveform 1 or specify clock period 3 Select a clock defined in Timing Settings 3 Select Clock 2

© 2000 Altera Corporation 178 Creating Counting Pattern Highlight waveform and enter pattern Highlight waveform 1 Pattern shortcut 2 Specify counting frequency 4 Specify counting pattern 3 Specify Radix 3 Select Count Value 2

© 2000 Altera Corporation 189 3rd Party Simulators VHDL Simulators –Use Quartus generated.VHO and.SDO files –Use APEX20K_ATOMs.VHD and APEX20K_COMPONENTS.VHD libraries located in the sim_lib directory Verilog Simulators –Use Quartus generated.VO and.SDO files –Use APEX20K_ATOMS.VO library located in the sim_lib

© 2000 Altera Corporation 196 Tcl/TK Console Console can be invoked using –View-> Auxiliary Windows-> Tcl/TK Console –Pressing the button Messages will appear in the Message Window under the System tab

© 2000 Altera Corporation 197 Command Line Mode Used for running Quartus in the batch mode Quartus command usage : –d:> \quartus\bin\quartus_cmd.exe - f Insert Tcl script in –Quartus is invoked from the DOS Prompt or the UNIX shell quartus_cmd.exe is the command to run Quartus from the command prompt. Using quartus.exe will bring up the GUI

© 2000 Altera Corporation 198 More Info : Command Line quartus_cmd -c –Compiles project with the specified Compiler Settings File (.csf) quartus_cmd -s –Simulates project with the specified Simulator Settings File (.ssf) quartus_cmd -h –Displays the help information for the Command Line

© 2000 Altera Corporation 199 More Info : Command Line Messages are written to DOS Window D:\testing > d:\Quartus\bin\quartus_cmd reg.quartus -c quartus.csf Info: Quartus Version 1999.06 A 2.4 6/21/1999 processing started at 06/23/99 09:09:33 Info: d:\testing\reg.bdf defines 1 design units and 1 entities. Info: Entity 1: reg Info: d:\testing\duplicate.bdf defines 1 design units and 1 entities. Info: Entity 1: duplicate Info: Logic Synthesizer created 4 element(s)... Info: 2 input pins Info: 1 output pins Info: 1 LCells Info: reg is automatically assigned to EP20K100TC144-1 Info: Fitting attempt 1 started at Wed Jun 23 1999 09:09:52 Warning: Timing characteristics of device EP20K100TC144-1 are preliminary Warning: Design has registers and/or memories but no clock assignments. Quartus will try to automatically detect your clock pins and/or memory enable pins Info: Node |clk is assumed to be a clock. Info: No valid register-to-register paths exist for clock |clk Info: reg: Full compilation was successful. 0 errors, 2 warnings. Completed...

© 2000 Altera Corporation 201 Quartus API Application Programming Interface (API) Functions –Pre-Defined Interface Functions The API allows for the following types of Tcl commands to interface with Quartus : –Project control functions Project Compiler Simulator –Device database functions Get device and timing information –Source code control functions Interface with Revision Control software

© 2000 Altera Corporation 202 Tcl/Tk Basics Tcl = Tool Command Language –Tk is an extension of Tcl, used for GUIs Works on PCs and Workstations Interpreted Programming Language Quartus uses Tcl/Tk version 8.0.3, supplied by Scriptics Quartus contains a Tcl text editor with syntax coloring

© 2000 Altera Corporation 203 Command Substitution –puts “The variable value is [expr $var + $var]” –Writes “The variable value is 6” to the Message Window Variable Substitution –puts “The variable value is $var” –Writes “The variable value is 3” to the Message Window Tcl Syntax Tcl is Case Sensitive Basic Syntax –command arg1 arg2 arg3 … –Example : set var 3 Sets variable “var” equal to 3 Name preceded by “$” is replaced with value of name Command within “ [ ] ” is replaced with results of command

© 2000 Altera Corporation 204 Controlling Projects with Tcl Tcl Project Commands can : –Create a Project –Open a Project –Close a Project –Check if a Project exists –Make Project Assignments –Get Project Assignments Tcl Project commands begin with the command “project” A listing of Tcl Project commands is found in the on-line help

© 2000 Altera Corporation 205 Making Project Assignments with Tcl Node or Entity Assignment –project add_assignment [entity] “” “” [node/entity name] [assignment type] [value] –Example : project add_assignment chiptrip “” “” |chiptrip|clock GLOBAL_SIGNAL ON Clique Assignment –project add_assignment [entity] [clique name] “” [instance name] MEMBER OF [clique name] –Example project add_assignment chiptrip clique1 “” auto_max|my_register MEMBER_OF clique1

© 2000 Altera Corporation 206 Controlling the Compiler with Tcl Tcl can access the Quartus compiler Tcl compiler commands can : –Start compilation –Stop compilation –Make compiler assignments –Get compiler assignments Tcl Compiler commands begin with the command “cmp” A listing of Tcl Compiler commands is found in the on-line help

© 2000 Altera Corporation 207 Making Compiler Assignments with Tcl Assign a device –cmp add_assignment [chip name] "" "" DEVICE [device] –Example : cmp add_assignment chiptrip "" "" DEVICE EP20K400BC652-3 Assign a pin –cmp add_assignment [chip name] "" [pin] LOCATION [device] –Example : cmp add_assignment chiptrip “” |clock LOCATION pin_U2

© 2000 Altera Corporation 208 Controlling the Simulator Via Tcl The Quartus simulator supports Tcl testbenches Tcl Simulation commands can : –Force and release values –Stop, Start, Pause simulation –Get debug info about the simulation –Read and write data from memory Tcl Simulation commands begin with the command “sim” A listing of Tcl Simulation commands is found in the on- line help

© 2000 Altera Corporation 209 Example Tcl Simulation Testbench project open chiptrip project set_active_sim chiptrip sim initialize while { [sim is_initialized] } { after 10;# sleep FlushEventQueue # flush messages } sim testbench_mode true sim print info “Simulation is initialized” sim force_value {dir\[0\]} 0# dir[0]=0 sim force_value {dir\[1\]} 1# dir[1]=1 sim force_value clock 0# clock = 0 sim run 10ns# simulate for 10ns sim force_value clock 1# clock = 1 sim run 10ns# simulate for 10ns sim get_value at_altera# get output value sim run end Time dir[0] dir[1] clock at_altera 0 0 1 0 X 10 0 1 1 0 20 0 1 1 0 Example Output File created by User Quartus does not create a graphical waveform of a Tcl Testbench “ get_value” writes text output to Tcl console output can also be piped to an output file using : puts $outputFile [sim get_value at_altera ] node/pin name

© 2000 Altera Corporation 210 Extending Quartus Tcl Commands Create procedures and libraries to customize and extend capabilities >> source.tcl >> example in1 in2.tcl proc example { input1 input2 } { … }

© 2000 Altera Corporation 211 Tcl Procedure for Base Clock Assignments # ------------------------------------------------------------------------------------------------------------------ # # Description:Add a base or absolute clock # add_base_clock [Clock Name] [Fmax] [Include Pin Delays in Calculation] [Duty Cycle] # # ------------------------------------------------------------------------------------------------------------------ proc add_base_clock {name fmax do_system duty} { if {$name != ""} { project add_assignment "" $name "" "" BASE_CLOCK $name } if {$do_system != ""} { project add_assignment "" $name "" "" DO_SYSTEM_FMAX $do_system } if {$fmax != ""} { project add_assignment "" $name "" "" REQUIRED_FMAX $fmax } if {$duty != ""} { project add_assignment "" $name "" "" REQUIRED_DUTY_CYCLE $duty }

© 2000 Altera Corporation 212 Using Tcl Base Clock Procedure Source.tcl add_base_clock mybase_clk 50MHz OFF 50 CLOCK(mybase_clk) { BASED_ON_CLOCK_SETTINGS = mybase_clk; INCLUDE_PIN_DELAYS_IN_CALCULATIONS = OFF; FMAX_REQUIREMENT = 50MHz; DUTY_CYCLE = 50; } Assignment gets stored in Project Settings File (.psf)

© 2000 Altera Corporation 213 Tcl Procedure for Relative Clock Assignments # -------------------------------------------------------------------------------------------------------------------------------- # # Description:Add a project relative clock # add_relative_clock [Clk Name] [Based on Clk] [* Base By] [/ Base By] [Base Offset] [Invert Base] # # -------------------------------------------------------------------------------------------------------------------------------- proc add_relative_clock {name base multiply divide offset invert} { if {$name != ""} { project add_assignment "" $name "" "" BASE_CLOCK $base } if {$multiply != ""} { project add_assignment "" $name "" "" MULTIPLY_BASE_CLOCK_BY $multiply } if {$divide != ""} { project add_assignment "" $name "" "" DIVIDE_BASE_CLOCK_BY $divide } if {$offset != ""} { project add_assignment "" $name "" "" OFFSET_FROM_BASE_CLOCK $offset } if {$invert != ""} { project add_assignment "" $name "" "" INVERT_BASE_CLOCK $invert }

© 2000 Altera Corporation 214 Using Tcl Relative Clock Procedure Source.tcl add_relative_clock new_clk_name mybase_clk 2 1 0 off CLOCK(new_clk) { BASED_ON_CLOCK_SETTINGS = mybase_clk; MULTIPLY_BASE_CLOCK_PERIOD_BY = 2; DIVIDE_BASE_CLOCK_PERIOD_BY = 1; OFFSET_FROM_BASE_CLOCK = 0; } Assignment gets stored in Project Settings File (.psf)

© 2000 Altera Corporation 216 For More Tcl Info Appendix “Quartus Tcl API” Quartus on-line help http://www.scriptics.com "Practical Programming in Tcl and Tk," Brent Welch. Prentice Hall, 1997. 2nd Ed. "Effective Tcl/Tk Programming," Mark Harrison and Michael McLennan, Addison-Wesley, 1997. "Tcl and the Tk Toolkit," John Ousterhout, Addison- Wesley, 1994.

© 2000 Altera Corporation 217 Summary Introduction to Altera & Altera devices Introduction to the Quartus development system Design Entry (review) Workgroup computing: Revision Control software Timing Analysis –Making timing assignments Floorplan Editor Simulation Scripting Review and Support

© 2000 Altera Corporation 218 Altera Technical Support Reference Quartus On-Line Help Consult Altera Applications (Factory Applications Engineers) –Hotline: (800) 800-EPLD (6:00 a.m. - 6:00 p.m. PST) –E-mail: Support@altera.com Field Applications Engineers: Contact Your Local Altera Sales Office Receive Literature by Mail: (888) 3-ALTERA FTP: ftp.altera.com World-Wide Web: http://www.altera.com –Use Atlas (Altera Technical Support) Solutions to Search for Answers to Technical Problems –View Design Examples –View Customer Training Class Schedule & Register for a Class

© 2000 Altera Corporation 222 Project Definitions Quartus Project: –A collection of related design files and libraries –Must have at least one designated top level entity –Targets a single device or can be partitioned into multiple devices –Stores project settings in Project Settings File (.PSF)

© 2000 Altera Corporation 224 4. Add design files - Graphic (.BDF,.GDF) - AHDL - VHDL - Verilog - EDIF Notes: All files in the project directory do not need to be added Add top level file if file name and entity name are not the same 5. Add user library pathnames and files Creating a New Project

© 2000 Altera Corporation 225 5(cont.) Add user library pathnames and files User Libraries (ex. MegaWizard functions) MegaCores/AMPP libraries Pre-compiled VHDL packages Browse to file and click on Add. Creating a New Project

© 2000 Altera Corporation 228 MAX+PLUS II to Quartus Converting MAX+PLUS II designs to Quartus: –Browse to project directory –Set top level file/entity –No need to add other files in directory –Add: Any files not located in same directory Any user directories as libraries Notes - Any Graphic Design File (.GDF) from MAX+PLUS II that is edited within Quartus can only be saved as a Block Diagram File (.BDF) by Quartus - Symbols with.GDF files may have to be updated - The Assignment & Configuration File (.ACF) from MAX+PLUS II is not recognized by Quartus

© 2000 Altera Corporation 229 Project Menu Edit the settings for an existing project –Adding/removing files or libraries Non-Wizard project settings –HDL interface –Third Party EDA Flow –Other settings discussed later Timing Revision Control Note: All Project settings except project name and top level entity default to the settings of the previously opened project

© 2000 Altera Corporation 231 Editing Project Settings To add/remove project files Adding - Browse to file - Click Add Removing - Select file from list - Click Remove Access via the General Settings dialog box

© 2000 Altera Corporation 233 VHDL Input Files Select VHDL version Enter Library names when directly compiling VHDL files with Quartus that contain user-created packages If gate level VHDL netlist file is used, specify mapping file (discussed later)

© 2000 Altera Corporation 236 Sample Project Settings File (PSF) DEFAULT_LOGIC_OPTIONS { DUPLICATE_LOGIC_EXTRACTION = ON; AUTO_TURBO_BIT = ON; AUTO_OPEN_DRAIN_PINS = ON; AUTO_PARALLEL_EXPANDERS = ON; AUTO_OUTPUT_REGISTERS = OFF; AUTO_INPUT_REGISTERS = OFF; AUTO_DELAY_CHAINS = ON; AUTO_CASCADE_CHAINS = ON; AUTO_CARRY_CHAINS = ON; PARALLEL_EXPANDER_CHAIN_LENGTH = 16; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN_LENGTH = 32; NOT_GATE_PUSH_BACK = ON; SLOW_SLEW_RATE = OFF; STATE_MACHINE_PROCESSING = AUTO; } DEFAULT_TIMING_REQUIREMENTS { IGNORE_REQUIREMENTS_FOR_FITTER = ON; CUT_OFF_IO_PIN_FEEDBACK = ON; CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; CUT_OFF_READ_DURING_WRITE_PATH = ON; } PROJECT_INFO(test) { } THIRD_PARTY_EDA_TOOLS(test) { } Default Logic Options (partial listing) Timing Analysis Information EDA Tool Information

© 2000 Altera Corporation 237 Project Navigator Graphical display used to study project relationships Active in both Compilation and Simulation modes Three views –Hierarchies view –Files view –Design Units view

© 2000 Altera Corporation 239 Views of the Project Navigator Files View –Shows all files in the project –All source files appear under Design Files –Simulation files, include files, etc., appear under Other Files

© 2000 Altera Corporation 240 Views of the Project Navigator Design Unit view –Displays each design unit a design entity that can be used together with gates, registers, and megafunctions in a design file –Displays type, e.g. AHDL entity –Details the File in which it is instantiated Design Unit Associated Design File

© 2000 Altera Corporation 241 Project Tips Use Project Wizard to create new projects Use Project Menu dialog boxes to –Edit existing project settings –Set up Third Party interface Use Project Navigator to study file and entity relationships within the project

© 2000 Altera Corporation 243 Controlling Synthesis & Fitting Compiler settings & assignments are used to control logic synthesis and place & route operations Most compiler settings & assignments are made after the initial compilation to resolve fit or performance issues Examples of assignments are: –Device Assignment –Pin Assignments –Synthesis Logic Options –Timing Requirements –Cliques

© 2000 Altera Corporation 244 What are Compiler Settings? Compiler control information –Device –Pin assignments –Level of compilation –Point of compilation in hierarchy –Synthesis & fitting –Verification Accessed via the Processing Menu Each contains a focus point (next slide) Information stored in a Compiler Settings File (.CSF)

© 2000 Altera Corporation 245 What are Focus Points? Design entities Points for compilation in a hierarchy –Entity is compiled as if it were the top level Top-level entity is the default focus point Focus Point A BCD E F

© 2000 Altera Corporation 246 Designers can work on sub-modules within a project without changing top level settings Can obtain fit & performance information for that particular entity Benefit of Compiler Settings Incomplete designs A BCD E F Focus Point Modules B, E, & F can be compiled even though Modules C & D are incomplete

© 2000 Altera Corporation 247 Hierarchy View –Displays Project Hierarchy after project is analyzed –Can be used to set and view focus points Focus Points Shows design entity is a project focus point Shows design entity is the current project focus point

© 2000 Altera Corporation 248 Compiler Settings Wizard (Steps 1, 2 & 3) 2. Select focus point 3. Select compiler settings name Note: Quartus defaults to Use to browse through hierarchy tree 1. Invoke Compiler Settings Wizard

© 2000 Altera Corporation 249 Compiler Settings Wizard (Steps 4 & 5) 4. Select compilation level - Netlist extraction only - Full compilation 5. Select Normal Compilation versus Smart Compilation Note: Must use Smart Compilation for incremental re-compilation.

© 2000 Altera Corporation 250 Compilation Types –Netlist extraction and synthesis only Compiler synthesizes gate-level code from design files Compiler stops after synthesis Compiler will generate estimated timing values only –Full compilation, including netlist extraction, synthesis, and fitting Compiler performs the above and fits the design into a device Compiler will generate actual timing values from device data and programming files Compilation Definitions

© 2000 Altera Corporation 251 Compilation Speed vs Disk Space –Normal compilation The Compiler will re-extract netlists only from design files that have changed Compilation uses less disk space but takes more time –Smart compilation The Compiler will save extra data in order to speed up future re- compilations Compilation takes less time but uses more disk space Compilation Definitions

© 2000 Altera Corporation 252 Compiler Settings Wizard (Step 6) 6. Do you want to assign a device? Note: Selecting “No” will turn on ‘Auto’ device selection which will choose the smallest device needed to achieve a fit

© 2000 Altera Corporation 255 Compiler Settings Wizard (Step 8 & 9) 8. Run timing analysis after compilation? 9. Run simulation after compilation? Note: This allows a user to initiate a simulation using the previously stored Simulator Settings selected

© 2000 Altera Corporation 257 Compiling in Quartus (Start) Perform Analysis & Elaboration (Save & Check) Perform Full Compilation (based on all compiler settings) - Compilation stops after file is analyzed for syntax errors 1

© 2000 Altera Corporation 260 Compiler Settings Menu Edit existing compiler settings –Change device –Change compilation level –Add/remove automatic timing analysis or batch simulation Non-Wizard compiler settings –Pin assignments –Timing-driven compilation

© 2000 Altera Corporation 264 Directs the compiler to synthesize & place logic to meet specified timing requirements Can optimize for I/O or internal timing Default is ON (option enabled) for both Compiler Settings - Timing Driven Compilation

© 2000 Altera Corporation 265 Stores compiler options for a particular module/entity Default file name is.csf Automatically created for top level entity Can be manually edited in Quartus New.CSF copies settings from previous.CSF Compiler Settings File (.CSF) Focus Point A BCD E F = modulea.csf = modulea_moduleb_modulef.csf

© 2000 Altera Corporation 266 Sample Compiler Settings File (.CSF) COMPILER_SETTINGS { FOCUS_ENTITY_NAME = |rfifo; RUN_TIMING_ANALYSES = ON; FAMILY = APEX20K; USE_TIMING_DRIVEN_COMPILATION = OFF; COMPILATION_LEVEL = FULL; SAVE_DISK_SPACE = ON; SPEED_DISK_USAGE_TRADEOFF = NORMAL; } CHIP(rfifo) { DEVICE = "EP20K100TC144-3"; AUTO_RESTART_CONFIGURATION = OFF; RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; USER_START_UP_CLOCK = OFF; ENABLE_DEVICE_WIDE_RESET = OFF; ENABLE_DEVICE_WIDE_OE = OFF; ENABLE_INIT_DONE_OUTPUT = OFF; ENABLE_LOCK_OUTPUT = OFF; JTAG_USER_CODE = 0XFFFFFFFF; CONFIGURATION_SCHEME = "PASSIVE SERIAL"; USE_CONFIGURATION_DEVICE_OPTIONS = OFF; USE_CONFIGURATION_DEVICE_NAME = EPC2LC20; CONFIGURATION_DEVICE_USER_JTAG_CODE = 0XFFFFFFFF; AUTO_INCREMENT_USER_JTAG_CODE = ON; DISABLE_CONF_DONE_AND_NSTATUS_ON_EPROM = OFF; GENERATE_TTF_FILE = OFF; GENERATE_RBF_FILE = OFF; GENERATE_HEX_FILE = OFF; HEX_FILE_START_ADDRESS = 0; HEX_FILE_COUNT_UP_DOWN = UP; RESERVED_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; NWS_NRS_NCS_CS_RESERVED = OFF; RDYNBUSY_RESERVED = OFF; DATA7_1_RESERVED = OFF; |aclr : LOCATION = PIN_10; } Compiler Control Settings Device & Device Options

© 2000 Altera Corporation 269 Node Finder 1. Select entity in which to search for nodes List of nodes in selected entity & lower levels of hierarchy 2. Use Filter to select the nodes to be displayed Note: Can create & save custom filter (next slide)

© 2000 Altera Corporation 272 Assignment Organizer 2. Choose assignment and setting 1. Click to add new assignment 3. Click Add to add assignment 3 types of Logic Options - Options for Individual Nodes Only - Options for Nodes and Entities - Options for Entities Only

© 2000 Altera Corporation 273 Assignment Organizer Categories Location –Specify Where to Place Logic in Device Timing –Add Timing Specifications to Improve Performance Clique –Place Selected Logic Together to Improve Performance Individual Logic Options –Individual Node –Individual Nodes, Groups of Nodes, or Entities –Entities Only

© 2000 Altera Corporation 274 Assignment Organizer Store in assignments for: –“This instance only” Stores assignment in the top- level.ESF Assignment made to only the selected instance –“This instance in all occurrences of its parent entity” Stores assignment in the.ESF for the entity one hierarchical level up Assignment applied to the selected instance whenever the parent entity is used –“All instances of this entity Stores assignment in a separate entity settings file for that entity Assignment applied to the selected instances wherever it is used in the project

© 2000 Altera Corporation 275 Assignment Organizer Store in assignments for: –“This instance only” Stores assignment in the top-level.ESF Assignment made to only the selected instance –“This instance in all occurrences of its parent entity” Stores assignment in the.ESF for the entity one hierarchical level up Assignment applied to the selected instance wherever the parent entity is used –“All instances of this entity” Stores assignment in a separate entity settings file for that entity Assignment applied to the selected instances wherever it is used in the project A BBC C C C C

© 2000 Altera Corporation 276 Assignment Organizer Store in assignments for: –“This instance only” Stores assignment in the top-level.ESF Assignment made to only the selected instance –“This instance in all occurrences of its parent entity” Stores assignment in the.ESF for the entity one hierarchical level up Assignment applied to the selected instance wherever the parent entity is used –“All instances of this entity” Stores assignment in a separate entity settings file for that entity Assignment applied to the selected instances wherever it is used in the project A BB C C C C C

© 2000 Altera Corporation 277 Assignment Organizer Store in assignments for: –“This instance only” Stores assignment in the top-level.ESF Assignment made to only the selected instance –“This instance in all occurrences of its parent entity” Stores assignment in the.ESF for the entity one hierarchical level up Assignment applied to the selected instance wherever the parent entity is used –“All instances of this entity” Stores assignment in a separate entity settings file for that entity Assignment applied to the selected instances wherever it is used in the project A BB C C C C C

© 2000 Altera Corporation 280 STATE MACHINE PROCESSING Encoding is on a machine by machine basis Each machine in the user’s design can be marked with one of the following logic options: –Auto: (Default) Use predetermined algorithm that is best for Family –Minimal Bits: The Compiler will force the minimum number of registers to encode the machine: No. of bits = LOG 2 (states) (Current MAX+plus II MAX algorithm) –One-Hot: The Compiler will force a one-hot encoding for the machine. (Current MAX+plus II FLEX algorithm) –User-Encoded: Use the user encoding if it is enough to decode the machine otherwise use auto encoding These options are not affected by the Pterm/LUT synthesis option

© 2000 Altera Corporation 282 TECHNOLOGY MAPPER Specifies which Technology Mapper to use: –LUT –PTERM –ROM –AUTO (PTERM or LUT) Best implementation of either PTERMS or LUT for performance Works on entire hierarchy User can choose a level if that hierarchy level and all its children will be mapped to PTERM or LUT Recommended to use for small hierarchies only Default value is LUT

© 2000 Altera Corporation 284 Stores synthesis and fitting assignments for nodes and entities File name is.esf Only created by Quartus if assignments are made Should not be manually edited Entity Settings File (.ESF)

© 2000 Altera Corporation 285 OPTIONS_FOR_INDIVIDUAL_NODES_ONLY { |datain[0] : FAST_INPUT_REGISTER = ON; |datain[1] : FAST_INPUT_REGISTER = ON; |datain[2] : FAST_INPUT_REGISTER = ON; |datain[3] : FAST_INPUT_REGISTER = ON; |datain[4] : FAST_INPUT_REGISTER = ON; |datain[5] : FAST_INPUT_REGISTER = ON; |datain[6] : FAST_INPUT_REGISTER = ON; |datain[7] : FAST_INPUT_REGISTER = ON; } OPTIONS_FOR_ENTITIES_ONLY { OPTIMIZATION_TECHNIQUE = SPEED; } Sample Entity Settings File (.ESF)

© 2000 Altera Corporation 286 The Compiler Report Contains all information on how a design was implemented in the targeted device –Device Summary Statistics –Compiler Settings –Floorplan Views –Device Resources Used –State Machines Implemented –Equations –Timing Analysis Results –CPU Resources This a read-only window

© 2000 Altera Corporation 287 Compilation Summary Use Compiler Wizard to create new Compiler Settings Use Compiler Settings dialog boxes to change existing compiler settings & make pin assignments Use Compiler Report to study design implementation and resource usage Use Assignment Organizer to assign logic options

© 2000 Altera Corporation 290 Introduction to Revision Control What is Revision Control? –Everyone does version control already Simply copying any files to another location Making comments of changes in design file –These are informal revision control methods Copying may not be applied consistently to different versions of a design file Keeping different file versions take up disk space Lack of documentation makes tracking changes difficult

© 2000 Altera Corporation 291 Benefits and Features of Revision Control Stores all project design files in one central location Store previous versions of the design files –Only stores changes between file versions to preserve disk space –Automatic back-up of design at different stages –Can call back last working version of a file checked in –Can compare changes between different versions of a file Reduces confusion as to which file is the most current file

© 2000 Altera Corporation 292 More Benefits and Features Creates a formal process of tracking changes to your design –Requires documentation for a design change via the log file –Info on who is working on a design file –Info on who has made changes to a design file Revision Control is necessary for multiple designers working on the same set of files –Arbitration of who can use or change a file –Prevents overwriting of design files when in this multi-user environment

© 2000 Altera Corporation 293 Revision Control System File B 1.0 File C 1.5 File A 1.1 Central Database Archive Database Log Files A,B,C Revision Control Software Workspace Engineer 1 Workspace Engineer 2 Workspace

© 2000 Altera Corporation 294 Revision Control System Central Database Archive - Keeps most recent copy of design file returned to archive, and older file versions Database Log Files - Keep track of all design changes –Who is using or has used the file –Changes to the design file for each version Revision Control Software - Arbitrates how a user can get a design file –Check out - read and write permission to a file –Check in - read only permission of a file –Latest copy - most recent version of file in central database Workspace - Location where designer will modify the file (Quartus project directory)

© 2000 Altera Corporation 295 Revision Control System Check out –File locked by user can only be edited by user –Other users can only get latest copy in central database (read only) –When returned, the file will be the latest version Get latest version –Locked by another user “Read only” copy from central database is available, but the user is aware that another user is editing the file –Not locked by another user “Read only” copy of last file checked in into the central database is available Get previous version –Can go into the archive and pull up an older version of a design file

© 2000 Altera Corporation 296 Revision Control System File B 1.0 File C 1.5 File A 1.1 Central Database Archive Workspace File A 1.2 File C 1.6 File A 1.1 File B 1.0 File B 1.0 Engineer 1 Workspace Engineer 2 Workspace Database Log Files A,B,C Revision Control Software

© 2000 Altera Corporation 297 Single-user Revision Control Revision Control still benefits single-users Essentially, same benefits of multi-user revision control –Only exception that no one will overwrite your design file(s) –Still track changes to your design –Still recover from unwanted design changes

© 2000 Altera Corporation 298 Quartus Interface Built in interface to common revision control software –PVCS (PC) –RCS (UNIX) –SCCS (UNIX) Also provides an interface to any revision control software –Advanced users, such as a CAD tool manager would be interested in this –Most other users would use off-the-shelf products like PVCS

© 2000 Altera Corporation 299 Quartus Interface How do I use revision control with Quartus? –Must purchase revision control software Quartus only provides the interface –Quick set-up with the the most common revision control software packages provided –TCL interface file for advanced users Provides support for other revision control packages Allows customization of in-house revision control packages Consult Source Code Control API for more info on this

© 2000 Altera Corporation 300 Setting up Revision Control Need a revision control software package Use the Revision Control Settings menu under Project pull down menu Set attributes of revision control software Select Revision Control software Select database where you want the design files to be stored

© 2000 Altera Corporation 301 Adding Files to Revision Control Commands are under Files tab in Project Navigator –Right click on design file for menu options –Add Current File to Revision Control Tcl/Tk command console can be used for other revision control commands

© 2000 Altera Corporation 302 Comment Log When adding a design file to database, Comment Log will appear Can monitor different revisions for various design files Can view log summary in Quartus Command Console window –# vlog

© 2000 Altera Corporation 303 Get files from Revision Control Database After files have been added to Revision Control database, file icon will appear in gray Right click on design file to bring up menu Check out files Get latest version of design file if file is locked by another user, in “read only” mode

© 2000 Altera Corporation 306 Other Revision Control Software Support 5 basic commands needed to support any package –Check-in (put file) –Check-out (get file with lock) –Get latest version (get read-only copy only) –Undo check-out (put file back without any changes made) –View log (see log file of changes) Outlined in Source Code Control API More advanced commands can be supported by TCL in Tcl/Tk command console –Log check (vlog) –File difference checks (vdiff)

© 2000 Altera Corporation 307 The Advanced User Needs to know Tcl/Tk to set-up interface Can use the SCC_PVCS.TCL file as a model for interfacing to other revision control tools –Will need a TCL debugger to test out TCL code –SCC_PVCS.TCL file located in bin directory

© 2000 Altera Corporation 308 Summary Revision Control is critical for multi-user design environments Allows for easy tracking of design file changes Convenient way to call back older versions of your design Automatically documents changes to your design

© 2000 Altera Corporation 1 Designing with Quartus.

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