1. Chapter 6 CPU Design

2. 6.1 Specifying a CPU A CPU performs the following sequences of operations (Figure 6.1) –Fetch cycle –Decode cycle –Execute cycle

3. Figure 6.1 Generic CPU state diagram

4. 6.2 Design and Implementation of a very simple CPU 1 word : 1bytes(8bit data bus) Address space: 64 bytes(6bit address bus) Instruction set: 4 (Table 6.1) Register: Accumulator(8-bit), AR(6-bit), PC(6-bit), IR(2-bit)

5. 6.2 Design and Implementation of a very simple CPU (continued) Fetch1: AR  PC Fetch2: DR  M, PC  PC+1 Fetch3: IR  DR[7..6], AR  DR[5..0]

6. Figure 6.2 Fetch cycle for the very simple CPU

7. Decoding Instructions Figure 6.3

8. Figure 6.3 Fetch and decode cycles for the very simple CPU

9. Figure 6.4 Complete state diagram

10. Executing Instructions ADD –ADD1: DR  M –ADD2: AC  AC+DR AND –AND1: DR  M –AND2: AC  AC^DR JUMP –JUMP1: PC  DR[5..0] INC –INC1: AC  AC+1

11. Regrouping the operations by each components AR: AR  PC; AR  DR[5..0] PC: PC  PC+1; PC  DR[5..0] DR: DR  M IR: IR  DR[7..6] AC: AC  AC+DR; AC  AC^DR; AC  AC+1

12. Establishing required data paths Figure 6.5

14. Reviewing the list of operations AR only supplies its data to memory IR does not supply data to any components. AC does not supply its data to any components The bus is 8-bits wide, but not all data transfers are not 8 bits AC must be able to load the sum of AC and DR and the logical AND of AC and DR. The modified version of Figure 6.5 is Figure 6.6

15. Figure 6.6

16. Design of a very simple ALU Figure 6.7

17. Figure 6.7 A very simple ALU

18. Designing the control unit using hardwired control Figure 6.8

20. Figure 6.9

21. Control Signals PCLOAD = JUMP PCINC = FETCH2 DRLOAD = FETCH1  ADD1  AND1 ACLOAD = ADD2  AND2 IRLOAD = FETCH3 MEMBUS = FETCH2  ADD1  AND1 PCBUS = FETCH1 READ = FETCH2  ADD1  AND1 Refer to Figure 6.10

22. Figure 6.10

23. Design verification Consider the code segment, containing each instruction once 0: ADD 4 1: AND 5 2: INC 3: JUMP 0 4: 27H 5: 39H The execution trace is shown in Table 6.4.

24. 6.3 Design and Implementation of A Relatively Simple CPU Specifications for a relatively simple CPU –Memory: 64Kbytes –Data width: 8-bit –Registers: AC[7..0], R[7..0], AR[15..0], PC[15..0], DR[7..0],IR[7..0],TR[7..0] –Zero flag –Instruction set: Table 6.5

25. Figure 6.11 fetch and decode cycles

26. Fetching and decoding FETCH1: AR  PC FETCH2: DR  M, PC  PC +1 FETCH3: IR  DR, AR  PC

27. Executing instructions NOP –NOP1: (no operation) LDAC; multiword instruction – opcode::lower-order half of the address:: higher-order half of the address –LDAC1: DR  M, PC  PC+1, AR  AR+1 –LDAC2: TR  DR, DR  M, PC  PC +1 –LDAC3: AR  DR,TR –LDAC4: DR  M –LDAC5: AC  DR

28. Executing instructions(continued) STAC; multiword instruction – opcode::lower-order half of the address:: higher-order half of the address –STAC1: DR  M, PC  PC+1, AR  AR+1 –STAC2: TR  DR, DR  M, PC  PC +1 –STAC3: AR  DR,TR –STAC4: DR  AC –STAC5: M  DR MVAC –MVAC1: R  AC MOVR –MOVR1: AC  R

29. Executing instructions(continued) JUMP –JUMP1: DR  M, AR  AR+1 –JUMP2: TR  DR, DR  M –JUMP3: PC  DR,TR JMPZ –JMPZY1: DR  M, AR  AR+1 –JMPZY2: TR  DR, DR  M –JMPZY3: PC  DR,TR –JMPZN1: PC  PC +1 –JMPZN2: PC  PC + 1

30. Executing instructions(continued) JPNZ –JPNZY1: DR  M, AR  AR+1 –JPNZY2: TR  DR, DR  M –JPNZY3: PC  DR,TR –JPNZN1: PC  PC +1 –JPNZN2: PC  PC + 1

31. Executing instructions(continued) OTHERS –ADD1: AC  AC+R, IF(AC+R=0)THEN Z  1 ELSE Z  0 –SUB1: AC  AC-R, IF(AC-R=0)THEN Z  1 ELSE Z  0 –INAC1: AC  AC+1,IF(AC+1=0)THEN Z  1 ELSE Z  0 –CLAC1: AC  0, Z  1 –AND1: AC  AC  R, IF(AC  R=0)THEN Z  1 ELSE Z  0 –OR1: AC  AC  R, IF(AC  R=0)THEN Z  1 ELSE Z  0 –XOR1: AC  AC  R, IF(AC  R=0)THEN Z  1 ELSE Z  0 –NOT1: AC  AC ’ IF(AC ’ =0)THEN Z  1 ELSE Z  0

32. Regrouping the data transfers AR: AR  PC; AR  AR+1;AR  AR,TR PC: PC  PC+1;PC  AR,TR DR: DR  M, DR  AC IR: IR  DR R:R  AC TR: TR  DR AC: AC  DR; AC  R,AC  AC+R; AC  AC-R; AC  AC+1; AC  0; AC  AC^R; AC  AC  R; AC  AC  R; AC  AC ’ Z: Z  1; Z  0

33. Figure 6.12 Complete state diagram

34. Figure 6.13 preliminary register set

35. Figure 6.14 generic bi-directional data pin

36. Page 246, Figure 6.15

37. Design of a relatively simple ALU All transfers that modify the contents of AC LDAC5: AC  DR MOVR1: AC  R ADD1: AC  AC+R SUB1: AC  AC-R INAC1: AC  AC+1 CLAC1: AC  0 AND1:AC  AC^R OR1: AC  AC  R XOR1: AC  AC  R NOT1: AC  AC ’

38. Design of a relatively simple ALU(continued) Rewriting the arithmetic operations to indicate the source of their operands LDAC5: AC  BUS MOVR1: AC  BUS ADD1: AC  AC+BUS SUB1: AC  AC-BUS INAC1: AC  AC+1 CLAC1: AC  0

39. Design of a relatively simple ALU(continued) Rewriting each operation as sum of two values and a carry LDAC5: AC  0+BUS+0 MOVR1: AC  0+BUS+0 ADD1: AC  AC+BUS+0 SUB1: AC  AC+BUS ’ +1 INAC1: AC  AC+0+1 CLAC1: AC  0+0+0

40. Figure 6.16 A relatively simple CPU

41. Figure 6.17 Hardwired control unit for the simple CPU

42. 6.4 Shortcomings of the simple CPUs More internal registers and cache Multiple buses within CPU (Figure 6.18) Pipelined instruction processing (Chapter 11) Larger instruction sets Subroutines and interrupts(Chapter 10)