1. Area: VLSI Signal Processing.
DESIGN AND PERFORMANCE ANALYSIS OF DIGITAL FILTER BASED ON MODIFIED FAST FIR ALGORITHM
Area: VLSI Signal Processing.
N.RAGULVASAN
Register No:
Project Guide: Ms. G. DURGA 1

2. MOTIVATION
The Low power designing structures and area efficient algorithms depended structures are more suitable for DSP application.
Pipelined and Parallel structures are major deign techniques.
Pipelined structure area increases by presence of delays.
The Parallel structure has more I/p and automatically area also increases & complied faster.
Parallel structure is effective and concurrency. 2

3. AREA ANALYSIS FFA:MUL=(2N-N/L), ADDERS=(2N-N/L+1)
Type of Filter
FFA based FIR filter structure
Modified FFA based FIR filter structure
Multipliers
Adders
24 tap 2 parallel FIR filter structure 36 37 30 42
72 tap 2 parallel FIR filter structure
108
109 90
126
144 tap 2 parallel FIR filter structure
216
217
180
252
FFA:MUL=(2N-N/L), ADDERS=(2N-N/L+1)
Modified FFA: MUL=(2N-N/L-N/2L), ADDERS= (2N-N/L+N/2L),

4. WORK DONE
The FIR filter structures are executed using parallel forms in order to increase speed and in this form area is major concern.
The area of filter is further reduced by modified FFA using the symmetric coefficients.
The modified FFA based FIR filter will be more useful in such a way to reduce the area.
The area and power analysis of FFA based FIR filter and modified FFA based FIR filter also done.

5. HIGHER ORDER MODIFIED FFA
The filter structure is divided into two ways namely pre-processing & post-processing blocks.
The pre-processing blocks can be followed by any type architecture.
The processing of a single sub-filter is reused of several levels.
The post processing blocks are combination of pre-processing and other sub-filter blocks together.
The higher order is given by 576 tap 4 parallel FIR filter structure.

6. OUTPUT FOR TRADITIONAL FFA

7. AREA REPORT

8. OUTPUT FOR MODIFIED FFA

9. AREA REPORT

10. WORK TO BE DONE
The proposed structure will be formed by LUT based multiplier.
The Area comparison of LUT memory size will be measured for both the Traditional and Modified FFA structures.

11. WORK PLAN

12. REFERENCE
Yu-Chi Tsao and Ken Choi, “Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 2, FEBRUARY 2012
C. Cheng and K. K. Parhi, “Hardware efficient fast parallel FIR filter structures based on iterated short convolution,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 8, pp. 1492–1500, Aug
C. Cheng and K. K. Parhi, “Further complexity reduction of parallel FIR filters,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS 2005),Kobe, Japan, May 2005.
C. Cheng and K. K. Parhi, “Low-cost parallel FIR structures with 2-stage parallelism,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.54, no. 2, pp. 280–290, Feb
Pramod Kumar Meher, Senior Member, IEEE, “LUT Optimization for Memory- Based Computation”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 4, APRIL 2010

13. THANK YOU