1. ECE 545 Project 2 Specification Part I

2. Adjust your synthesizable code for Project 1 in such a way that it complies with the following requirements: a. your code implements the function of the encryption/decryption unit of RC5 without without key scheduling unit, and without memory of round keys. b. your code has an exact interface shown on the next slide c. your code can be synthesized using Synopsys and TSMC libraries of standard cells for at least the following two sets of RC5 parameters a. RC5 16/24/16 b. RC5 32/12/16 Task 1

3. Encryption/decryption unit with control & i/o interface clock reset encrypt/decrypt data input data available data read 2w data output write full round number i round key S[2i] round key S[2i+1] 2w2w w wlog 2 (r+1) d. your code implements basic iterative architecture of RC5 and is optimized for the maximum throughput to area ratio. RC5 circuit interface

4. Prepare a comprehensive testbench capable of verifying the operation of your entire circuit. This testbench should read test vectors containing a. inputs b. round keys, and c. corresponding outputs from a text file. All values should be stored in the hexadecimal notation. Verify the function of your circuit using this testbench. Task 2

5. Synthesize your code for the following two values of of the RC5 parameters a. RC5 16/24/16 b. RC5 32/12/16, using the following tools and libraries: 1.Synopsys with the 90 nm TCBN90G TSMC library 2.Synopsys with the 130 nm TCB013GHP TSMC library 3.Synplify Pro using the smallest device of the Xilinx Spartan 2 family capable of holding the larger of the two RC5 circuits. Analyze, compare, and discuss the obtained netlists. Task 3

6. For all synthesized circuits, determine maximum clock frequency maximum encryption/decryption throughput area ratio: maximum encryption/decryption throughput divided by area. Compare, discuss, and explain results obtained for all analyzed cases. Task 4