1. Simulation & Synthesis of UART HD-6402 using VHDL [02-384] Deepak Patel Presented by

2. Scope of our Project

3. VLSI and its Emergence

4. Chip Complexity 1975: transistor size = 10  m 1985: transistor size = 2  m 1995: transistor size = 0.4  m

5. Introduction to VHDL

6. Design Process

7. Required product Design specifications Initial design Simulation Design correct? Redesign Prototype implementation Testing Meets specifications ? Finished product Minor errors? Make corrections No Yes No Yes No

8. Concept of Design Review Design Specifications Simulation RTL Simulation Synthesis Description Verify Synthesis Results Timing Analysis Implementation( FPGAs, ASICs )

9. UART Basics for our project

10. Communication system Source Transmitter Encoder Receiver Decoder Destination Channel

11. Asynchronous Communication Start Bit Stop Bit 8 Data Bits Mark Space

12. What is UART ? niversal synchronous eceiver ransmitter

13. Basic UART Interface PARALLEL DATA BUS UARTUART PP External Device

14. Need for UART To convert the parallel data from  P systems to serial data to external devices Or vice-versa. It is necessary to have an interfacing device. External devices are capable of communicating only serially Computer and  P systems often send/receive data in parallel format

15. Block Diagram of UART

17. Control Word

18. Advantages of Implementing UART using VHDL

19. How Stuff works ???

20. PARITY FUNCTION CLS2CLS1DATA LENGTH 005 BITS 016 BITS 107 BITS 118 BITS CLS2 CLS1 8 BIT DATA PARITY GENERATOR PARITY BIT

21. TRANSMITTER CLS2CLS1 PI EPE SBS P1: If CRL is High load CONTROLWORD P2: 0 to 5 Bits 1 to 2 Bits 0 or 1 Bit 5 to 8 Bits 1 Bit Extra bits Stop bits Parity bits Data bits Start bits

22. P3: Generation of TRE, TBRE. CLS2CLS1 PI EPE SBS If CTRLWORD is 000X0 counter = 8 If CTRLWORD is 000X1 counter = 9 Shifting 12 bit contents to right bit by bit. Transmit serial Data at TRO pin.

23. RECEIVER CLS2 CLS1 SBS PI EPE P1: If CRL is High load CONTROLWORD. Receive data from transmitter bit by bit. P2: To see that data is not overwritten with the help of DR pin. To store each bit serially in a register. 11109876543210 If CONTROLWORD is 0001X => 1 start 5 data 0 parity 1 stop So 5 th bit is checked and if 0 then DR is set Data In Data Out

24. P3: In it valid data is send into receiver register and extra zeros are padded. If CONTROLWORD is 0001X =>1 start 5 data 0 parity 1 stop So valid data bits are from 10 to 6. P4: In it PE, FE, OE are generated. If CTRLWORD is XX101- check 9 th bit. If CTRLWORD is XX001- check 10 th bit. If CTRLWORD is XX0XX- check 11 th bit for Stop bit. If CTRLWORD is XX1XX- check 10 th and 11 th bit for Stop bit. P5: Sends 8 Bit data to RBR and sends error output to output pins. CLS2 CLS1 SBS PI EPE 1110 9 8 7 6 5 4 3 2 1 0 Data In Data Out