1. Error Correction and Partial Information Rewriting for Flash Memories Yue Li joint work with Anxiao (Andrew) Jiang and Jehoshua Bruck

2. Block Erasure is Harmful Decreasing cell level triggers block erasure – Erasure degrades cell quality 2 E. Cohen, “The Nibbles and Bits of SSD Data Integrity”, Flash Memory Summit, 2013.

3. Solutions based on Coding 3 Error Correcting Codes Trajectory Codes[8] Codes for Rewriting Floating Codes [2] Buffer Codes [3] Rank Modulation [4] WOM [5, 6, 7] Codes for Rewriting Floating Codes [2] Buffer Codes [3] Rank Modulation [4] WOM [5, 6, 7] [8] A. Jiang, M. Langberg, M. Schwartz, and J. Bruck, "Trajectory Codes for Flash Memory,” IEEE Transactions on Information Theory, vol. 59, no. 7, pp. 4530-4541, July 2013. [2] A. Jiang, V. Bohossian, and J. Bruck, "Floating Codes for Joint Information Storage in Write Asymmetric Memories,” ISIT, 2007. [3] V. Bohossian, A. Jiang, and J. Bruck, "Buffer Coding for Asymmetric Multi-Level Memory,” ISIT 2007. [4] A. Jiang, R. Mateescu, M. Schwartz, and J. Bruck, "Rank Modulation for Flash Memories,” IEEE Transactions on Information Theory, 2009. [5] R. L. Rivest and A. Shamir, “How to reuse a ‘Write-Once’ memory,” Information and Control, vol. 55, pp. 1–19, 1982. [6] E. Yaakobi, S. Kayser, P. H. Siegel, A. Vardy, J. K. Wolf, "Codes for Write-Once Memories,” IEEE Transactions on Information Theory, 2012. [7] D. Burshtein, and A. Strugatski, "Polar Write Once Memory Codes,” IEEE Transactions on Information Theory, 2012. [2] A. Jiang, V. Bohossian, and J. Bruck, "Floating Codes for Joint Information Storage in Write Asymmetric Memories,” ISIT, 2007. [3] V. Bohossian, A. Jiang, and J. Bruck, "Buffer Coding for Asymmetric Multi-Level Memory,” ISIT 2007. [4] A. Jiang, R. Mateescu, M. Schwartz, and J. Bruck, "Rank Modulation for Flash Memories,” IEEE Transactions on Information Theory, 2009. [5] R. L. Rivest and A. Shamir, “How to reuse a ‘Write-Once’ memory,” Information and Control, vol. 55, pp. 1–19, 1982. [6] E. Yaakobi, S. Kayser, P. H. Siegel, A. Vardy, J. K. Wolf, "Codes for Write-Once Memories,” IEEE Transactions on Information Theory, 2012. [7] D. Burshtein, and A. Strugatski, "Polar Write Once Memory Codes,” IEEE Transactions on Information Theory, 2012.

4. Write-Once Memory Codes R. L. Rivest and A. Shamir, “How to reuse a ‘Write-Once’ memory,” Information and Control, vol. 55, pp. 1–19, 1982. Data Codeword (1 st write)Codeword (2 nd write) 00000111 01001110 10010101 11100011 Write 2 bits twice using 3 cells 000 010 110 4 Example: store 10 then 01

5. General Rewriting Graph 5 7 7 6 6 5 5 4 4 3 3 2 2 0 0 1 1 Directed, Strongly Connected Graph G(V, E) Data State Allowed Transition

6. A message M 0 is updated K-1 times following (M 1, M 2, …, M K-1 ) Sum Rate = K log 2 |V| / N (bits/cell) Total number of cells Total number of message bits 6 Example: for R-S WOM code, K = 2, |V| = 4, N = 3. Sum Rate = 4 / 3 = 1.33 bits / cell > 1 bit/cell Example: for R-S WOM code, K = 2, |V| = 4, N = 3. Sum Rate = 4 / 3 = 1.33 bits / cell > 1 bit/cell Performance Measure

7. General Rewriting Graph 7 7 7 6 6 5 5 4 4 3 3 2 2 0 0 1 1 Directed, Strongly Connected Graph G(V, E) Data State Allowed Transition Partial Maximum outdegree << |V|

8. Motivation of Partial Rewriting Server A A B B C C Remote File Synchronization Update Synchronization Dropbox or Mobile App Server Dropbox or Mobile App Server 8

9. BSC(p) Trajectory Codes 0 a0 a0 b a5 b 0 0 1 1 2 2 ab 5 5 a … 9 Store 0 1 2 5 Update to [1] A. Jiang, M. Langberg, M. Schwartz, and J. Bruck, "Trajectory Codes for Flash Memory,” IEEE Transactions on Information Theory, vol. 59, no. 7, pp. 4530-4541, July 2013. Register A register is a group of cells Register A register is a group of cells log 2 |V| bits log 2 |D| < log 2 |V| !! BSC(p) for Noisy Cells A register goes through a BSC(p) between two updates. ?

10. Construction 1 (Example: C = 3, t = 2, K = 6) 0 0 0 1 1 2 2 ab 5 5 a … 10 Write 0 Corrects BSC(p *3 ) Corrects BSC(p *2 ) Corrects BSC(p) 0 Update to 1 a BSC(p) 0 Update to 2 a b BSC(p) 0 Update to 5 a b BSC(p) 5

11. Bounds on Achievable Code Rates 11 Sum Rate = K log 2 |V| / N (bits/cell) N = N 0 + N 1 + … + N c-2 + N c-1 N 0 = log 2 |V| / min j R 0,j N i = log 2 D / min j R i,j if i > 0 Upperbounds and lowerbounds of R 0,j and R 0,j can be derived with Polar ECC-WOM [2] [2] A. Jiang, Y. Li, E. En Gad, M. Langberg, and J. Bruck, “Joint Rewriting and Error Correction for Write-Once Memories,” ISIT, 2013. Instant rate of the j-th write of the i-th ECC-WOM code

12. Performance of Construction 1 Compare the bounds of three cases – Max degree: D is larger 2 1024 – D is smaller 2 13 – Basic ECC-WOM using only 1 register Parameters – Message length: log 2 |V| = 1KByte (2 13 bits) – Number of registers: C = 8 – Channel error rate p = 10 -3 12

13. Performance of Construction 1 13

14. Construction 2 (Example: C = 3, t = 2, K = 6) 0 S0S0 0 0 1 1 2 2 ab 5 5 a … Write 0 Corrects BSC(p) BSC(p) a, S 0 + S’ 0 0 1 S’ 0 BSC(p) a, S 0 + S’ 0 0 2 S’’ 0 S1S1 S’ 1 b, S’ 0 + S’’ 0, S 1 + S’ 1 BSC(p) a, S 0 + S’ 0 0 Read 2 S’’’ 0 S’’ 1 b, S’ 0 + S’’ 0, S 1 + S’ 1 S2S2 BSC(p) S’ 2 Recover S 1 by decoding S’ 1 = S 1 + BSC(p)Recover S 0 by decoding (S’’ 0 + (S 0 + S’ 0 )) = S 0 + BSC(p) Recover S 0 by decoding S’ 0 = S 0 + BSC(p) Recover S 2 by decoding S’ 2 = S 2 + BSC(p)Recover S 1 by decoding (S’’ 1 + (S 1 + S’ 1 ))= S 1 + BSC(p) Recover S 0 by decoding (S’’’ 0 + (S 0 + S’ 0 ) + (S’ 0 + S’’ 0 ))= S 0 + BSC(p)

15. Performance of Construction 2 15

16. Generalizations When t = 1and M 0 = M 1 = … = M K-1 – Erasure-free memory scrubbing [3] – Error correction pointer [4] 16 Information Storage Area Error Logging Area [3] Y. Li, A. Jiang, and J. Bruck, ”Multiphase Scrubbing for Phase-Change Memories,” Technical Report, 2013. [4] S. Schechter, G. Loh, K. Straus, and D. Burger, “Use ECP, not ECC, for hard failures in resistive memories.” In Proceedings of the 37th annual international symposium on Computer architecture (ISCA '10), 2010. [3] Y. Li, A. Jiang, and J. Bruck, ”Multiphase Scrubbing for Phase-Change Memories,” Technical Report, 2013. [4] S. Schechter, G. Loh, K. Straus, and D. Burger, “Use ECP, not ECC, for hard failures in resistive memories.” In Proceedings of the 37th annual international symposium on Computer architecture (ISCA '10), 2010.

17. Generalizations (2) Error correction support for all kinds of rewriting codes! 17 WOM [5,6,7] Floating Codes [2] Buffer Codes [3]

18. Summary Error correction trajectory codes are – Efficient when D << |V| – General Existing practical memory scrubbing/ECP schemes Error correction for various rewriting codes – Extensible q-ary ? Asymmetric noise channel ? Capacity ? 18