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Module Development Plan I believe that we are ready to proceed to a program to demonstrate a PS module based on “2.5 D” interconnections. This is based.

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Presentation on theme: "Module Development Plan I believe that we are ready to proceed to a program to demonstrate a PS module based on “2.5 D” interconnections. This is based."— Presentation transcript:

1 Module Development Plan I believe that we are ready to proceed to a program to demonstrate a PS module based on “2.5 D” interconnections. This is based on 1.A ROIC which contains electronics for both the strip and pixel tier 2.An interposer that adapts the pitch of the pixel sensor to the ROIC, carries digital signals and DC_DC converter and GBT 3.Carbon foam sandwich structure 4.Flex foldover to carry long strip signals to top tier R. Lipton1

2 Proposed Structure R. Lipton2 Top sensor bottom sensor Flex interconnect To PCB PCB/flex ROICs The overlapped sensor on the bottom allows for all of the assembly operations to be done on a plane except for the final foldover An extended overlap could solve the issue of z communication by extending the long strips into the other half

3 Technical Issues We need to make space for digital signals as well as provide space between chips. This involves rerouting signals. The current design gangs the pixels near to module center and routes an additional set of channels outboard. – This requires fine pitch signal routing and through vias – marginal for PCB, but “easy” for silicon interposer R. Lipton3 Sensor pixels Inner bottom bump Through vias Inner top bump

4 Prototyping I have talked to a few companies which appear to have the capability to manufacture the interposers on PCB (R&D circuits, Endicott interconnect) or on Silicon (RTI, Allvia). Also discussed bump bonding with Engent inc. Feature needed to make the PCB solution work is via-in pad, which allows space for the larger vias in PCBs Fine pitch in silicon interposer can provide more sophisticated routing Rigid/flex does not appear to support fine enough pitch – use separate flex for now Bump bonding is a key issue – we need 2 layers of bumps. Is the CTE difference in the PCB solution a deal-breaker? R. Lipton4 TypeLines & SpacesViasCTE (ppm/deg) PCB 50  >100  10-14 Silicon 10  25-30  3

5 Suggested Plan Send PCB and silicon interposer designs for prototype fabrication soon – I think there is a workable design concept, but it needs input and review. The tsv design gds file is posted on the agenda page Design and fabricate daisy chain test dummy sensors and ROICs that can be used to verify bonding connections (use bond pads at the outer edges as test points) – Need to define this responsibility Bump bond prototype assemblies – probably in industry – Thermal and mechanical tests Study the mechanical assembly and thermal properties of carbon foam-based modules – Both mockups and FEA R. Lipton5

6 6 DC-DC 1 of 16 ICs 1 of 16 ICs Top view of board GBT

7 R. Lipton7 Top sensor Flex interconnect To PCB PCB/flex ROICs bottom sensor Readout interconnect

8 R. Lipton8 Top sensor PCB/flex ROICs bottom sensor ROICs Digital bus area Digital I/O


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