1. On-Chip Sensors for Process, Aging, and Temperature Variation
Kaushik Mazumdar
Jared Robertson

2. Overview Motivation Existing Methods Test Circuit Simulations Summary
References

3. Motivation Local Process Variation Global Process Variation
Temperature Variation
NBTI/PBTI Degradation
[1]

4. Existing Methods Device Array Ring Oscillator Large Area
Long Test Time
Many I/O Pins
Ring Oscillator
Doesn’t Measure Mismatch or Variation Gradients
Can’t Measure PMOS/NMOS Variation Separately
[2]

5. Weak Pull-down / Strong Pull-up Strong Pull-down / Weak Pull-up
Sensor Circuit
Virtual Gnd
Virtual Vdd
Weak Pull-down / Strong Pull-up
203.5 mV
1.091 V
Strong Pull-down / Weak Pull-up
25 mV
965.4 mV
[3]

6. Simulation Used Monte Carlo to randomly vary Vt in transistors
PMOS 1
PMOS 2
PMOS 3
PMOS 4
PMOS 5
Process 1
3.685
4.0063
4.2199
4.286
4.216
Process 2
3.5464
3.807
4.0457
4.0708
4.0807
Process 3
3.5092
3.7241
4.0478
3.9348
4.0488
Process 4
3.4925
3.7479
4.0309
3.9846
4.0536
Process 5
3.4494
3.7377
3.9398
3.9752
4.027
Used Monte Carlo to randomly vary Vt in transistors
Extracted frequency of ring oscillator for each active header/footer over various process runs
Extracted statistical data from frequency values

7. Threshold Voltage Extraction
Random variability and systematic shift can be measured from data
Use equation derived from simulation to calculate device-level variations with oscillator frequency

8. Sensitivity Knobs
Circuit is more sensitive to process variation when header/footer sizing is minimized
Circuit becomes more sensitive to process variation as number of oscillator stages increases

9. To Maximize Process Variation Sensitivity
Sensitivity Knobs
Circuit is more sensitive to process variation at higher Vdd
Set knobs to maximize sensitivity for process variation
Placing many sensors around the chip exploits the increased sensitivity for fewer ring oscillator stages
To Maximize Process Variation Sensitivity
Vdd
# Stages
Header/Footer Sizing
High
Low
Minimum

10. Process Variation Sensitivity
Thermal Sensor
The oscillator can be stretched across a chip to sense temperature variation
Process variation sensitivity should be minimized
Our simulations achieved a sensitivity reduction of 10x
Process Variation Sensitivity
Vdd
# Stages
Header Sizing
Standard Deviation
Maximum
1.1 11
90nm
0.1281
Minimum
0.7 23
300nm
0.0126

11. NBTI/PBTI Sensor Frequency Sensor Measures Beat Frequency
Differential Measurement Method Isolates NBTI/PBTI Degradation from other variation sources
[4]

12. Odometer Output

13. Summary Analyzed variation issues and existing solutions
Showed simulation methodology and results
Tuned oscillator circuit to isolate process variation from temperature
Displayed how circuit can be used as a temperature sensor
Developed NBTI/PBTI degradation detection method
Discussion of possible future work

14. References
M. A. Alam, S. Mahapatra, "A comprehensive model of PMOS NBTI degradation," Microelectronics Reliability, vol. 45, pp , 2005.
Kanak Agarwal; Kanak Sani Nassif; “Characterizing process variation in nanometer CMOS”, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California.
Agarwal, Kanak, “On-die sensors for measuring process and environmental variation in integrated circuits.” IBM Corps. Austin, TX
Tae-Hyoung Kim; Persaud, R.; Kim, C.H.; "Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits," Solid-State Circuits, IEEE Journal of , vol. 43, no. 4, pp , April 2008.
Wei Zhao; Liu, F.; Agarwal, K.; Acharyya, D.; Nassif, S.R.; Nowka, K.J.; Yu Cao; , "Rigorous Extraction of Process Variations for 65-nm CMOS Design," Semiconductor Manufacturing, IEEE Transactions on , vol.22, no.1, pp , Feb
Kumar, R.; Kursun, V.; , "Temperature Variation Insensitive Energy Efficient CMOS Circuits in a 65nm CMOS Technology," Circuits and Systems, MWSCAS '06. 49th IEEE International Midwest Symposium on , vol.2, no., pp , 6-9 Aug