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Implementing Sequential Circuits ECE555: Digital Circuits and Components Instructor: Azadeh Davoodi
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2 Consider the following circuit: Strong positive feedback Inverter is high gain Only stable in 1 of 2 states: n1=VDD, n2=VSS n1=VSS, n2=VDD Bi-stable circuit n1 n2 So cross-coupled inverters could form a memory element Will hold the last state that was put in Now we just need a method to “write it”
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3 D EN Q Consider the circuit above. What problems might it have? fb fftg D EN Q fb fftg n1 0V 5V 0V 5V If the latch is currently holding 0V at n1 then we try to write a “1” to n1 what will happen? Consider body effect on tg n1 is likely best case to get to around 3.2V with body effect Consider that the n-device in fb is fighting the transfer gate
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4 D EN Q fb fftg n1 0V 5V 0V 5V Given the fact that fb is contending with the transfer gate on a write, how would you size (W/L) the devices inside inverter fb -Need to downsize all W/Ls inside fb, keeping P/N ratio the same. This creates a “weaker” device indicating it has a lower drive strength (IDS). The drive strength to node n1, however, is also a function of the drive strength of what is driving into the D input -As long as the “strength of D” is higher than fb, n1 can be rewritten. Given the V T drop involved in driving node n1, how would you size the (P/N) ratio of inverter ff - Size P/N ratio to decrease RN and increase RP to get more voltage drop when the output off should be LOW. Now, how do you think this would work at a 2.5V VDD. - Probably won’t work due to body effect for this lower level of VDD! How would you fix this problem. See next slide
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5 D EN Q fb fftg n1 0V 5V 0V 5V This latch will work at 2.35V and lower, however one needs to be careful with its use regarding two issues: 1) Drive strength of input to overcome the contention of the fb path. 2) Loading on output to avoid a charge share write back (cover this later). How could we solve the contention problem of the feedback path? (besides the potential functional drawback of the contention in the feedback, it also creates additional current consumption when writing a new value)
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6 D EN Q n1 By adding a transmission gate within the feedback, contention is solved and there is no need to upsize the feedback inverter (fb). This latch topology was very popular for a long time and is still used, however, it does have the following weaknesses. (1) One weakness is a susceptibility to “charge share back writing” (will explain later). (2) Another weakness is to a victim/attacker event on the output. To explore that we first have to speak of interconnect capacitance.
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7 Line to Line coupling increasing with modern processes. Older processes had wider and shorter (less height) metals with more interconnect spacing As metal widths shrunk, the heights were increased to try to maintain the same resistance, and the spacing also reduced with technology scaling. This resulted in significant line to line capacitance. Problems with interconnect on modern processes will be covered more in detail later in future lectures.
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8 D EN n1 0V 5V C LL 5V 0V Victim/Attacker event in the output: Signal running parallel to your output makes a quick 5V 0V transition. This pulls a quantity of charge out of the output of the latch thus causing it to have a lower voltage level. If this dipping in the voltage goes below (VDD-V T ) of inverter fb, it will start to raise n1. If n1 gets above the V T of inverter ff the whole memory loop will flip. fb ff
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9 D EN n1 0V 5V fb ic=0V 0V 5V Another issue: Charge Share Back Writing problem Latch is driving into a passgate circuit. Diffusion load on other side of passgate is high, and charged the opposite of the output of your latch. When the passgate closes, again there is a quantity of charge “sucked off” the output of the latch, causing the output to dip.
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10 Most common problem with having the output in the memory loop: D EN n1 0V 5V fb CLCL To write the latch to the opposite state, the output (Q) has to transition through the switch point of the feedback inverter fb during the transparency window. If C L is large, the output could have a slow slope. Now the setup time of the latch becomes a function of C L. This is unacceptable.
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11 D EN n1 fb How can you solve these problems so that a disturbance in the output node does not change the contents of the latch, and from C L affecting the setup time? Buffer the output (Q) separate from the “memory loop”. Now a disturbance on Q does not enter the loop. Q
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12 Trouble with passgate inputs V T also lowers with advanced processes D EN n1 fb Q 2.5V 0V 0V 2.5V 0V Consider the scenario where the input is 0V, the latch is not Enabled, and it is holding a logic high (2.5V in this example) at node n1 A line running parallel with significant line to line coupling switches low. This couples the input to the latch negative. Now the n-device of the passgate sees a positive V GS, conducts, and may write node n1 to a logic 0. C LL
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13 How would you solve this problem? Add a buffer right after the D input. D EN n1 fb Q What is the right balance of robustness vs size? We started with a 5-transistor latch Then made passgate fully complementary, 8-transitor Then added passgate to tri-state the feedback, 10-transistor Then added output inverter to isolate the memory loop, 12-transistor Then added input inverter to avoid passgate input, 14-transistor
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14 The last fix only fixes problems for extreme situations of line to line coupling and fast slope “attackers” in the input line. 99.99% of all cases may not require this “fix”, so should we pay the extra penalty (extra transistors) in every copy of the latch/flop? This is not an easy question. Depends on design philosophy. Only takes 1 case to create a “hard to find” failure. Still perhaps our CAD tools can be made to look for these cases. Robustness vs Size
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15 Another look at the contention in the feedback path. p-devices are weak relative to n-devices. The contention in the feedback path was mainly a problem for writing a logic 1 to the contending node. So inverter fb can be replaced by a “weak” PMOS. D EN n1 Q In this new design, there will be some contention when writing a logic 0 to n1, however p-devices are inherently weak and easy to contend against so we accept such a contention in return for saving an NMOS (in the removed inverter fb). To keep logic 0 at n1, the NMOS stack is added. The stack also ensures that when writing a logic 1 to n1, the n-device stack is shut down, hence there is no contention.
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16 Now for making a flop from our latch design: D clk Q Q A little smaller than two latches (saving two inverters) Separate output inverter on master latch (to separately provide QM) not needed since we are in a controlled environment (we know the load is the slave latch and not any CL that a designer may arbitrarily introduce) Inverter for creating clk can be shared.
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17 Remember the pulse latch Idea? How do we make that? GCLK CLK Delay = pw GCLKd_n GCLK GCLKd_n CLK pw
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18 If you added the above “one-shot” circuit to every latch to create a pulse latch you wouldn’t realize any area or power savings. Need to “amortize” the cost of the one-shot circuit over many sequential elements to realize the true advantage of using pulse latches. In practice this is easily done on a large chip because you normally distribute a global clock (GCLK) which is locally buffered (LCB) To form the clock that feeds your sequential elements. GCLK CLK01 CLK02 CLK03 CLK04 Local Clock Buffer (LCB) Now simply replace these LCB’s with one-shot LCB’s and you have the pulse clock network you need.
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19 Measuring t SU and clk2q for a flop: As one pushes (decreases) the setup time, the flop will not immediately transition to hard failure. Instead the clk2q will begin to push out (increase). Eventually a hard failure will occur, but prior to that there is a point at which the quantity (t SU + clk2q) is minimized. The above experiment can be setup by doing a voltage sweep on the D input of an unknown flop and identifying the point right before a failure is observed in the out put (i.e., the point when input before the clock is not “sampled” in the output after the clock). This is the point used to measure the true t SU and clk2q tSU will be the propagation delay from the input slope (corresponding to this point) to the clock edge Clk2q will be the propagation delay from the clock edge to the output slope (corresponding to this point)
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