1. CMS Phase 2 Pixel Electronics meeting – 27/01/2015 Status and plans of pixel electronics simulation framework Elia Conti – PH-ESE

2. 2/8 CMS Phase 2 Pixel Electronics meeting – 27/01/2015 OUTLINE Goal VEPIX53 environment – current version Example: study of trigger latency buffering architectures Current plans

3. Goal RD53 simulation working group: flexible simulation and verification framework as essential high level development tool –system level –building blocks (IP) level [Christiansen, Garcia-Sciveres, CERN-LHCC-2013-008] Requirements –flexible generation of input stimulus –constrained-random + directed tests (extreme cases) –imported from sensor/MC simulations –combination of the two –simulation at different levels of description –automated verification –statistics on performance –generation and classification of warnings/errors –same environment for different design flow steps CMS Phase 2 Pixel Electronics meeting – 27/01/2015 3/8

4. VEPIX53: Verification Environment for RD53 PIXel chips Implemented in SystemVerilog + UVM library (advanced verification features) –hit generation and injection –monitoring of pixel chip input and output –conformity checks and statistics collection VEPIX53 environment – current version (I) [Marconi et al., J. Instrum., 2014] CMS Phase 2 Pixel Electronics meeting – 27/01/2015 4/8

5. VEPIX53: Verification Environment for RD53 PIXel chips Implemented in SystemVerilog + UVM library (advanced verification features) –hit generation and injection –monitoring of pixel chip input and output –conformity checks and statistics collection VEPIX53 environment – current version (II) CMS Phase 2 Pixel Electronics meeting – 27/01/2015 5/8 [Marconi et al., J. Instrum., 2014] Interaction point Sensor α Single particles JetsLoopers Machine background Different classes of parameterized hits

6. Example – study of trigger latency buffering architectures PUC PR SHARED BUFFER... PR OUTPUT PIXEL REGION (PR) PIXEL UNIT CELL (PUC) TRIGGER [Conti et al., TWEPP, 2013] –Trigger latency buffer: critical section of pixel chip system –Efficient processing of hits by grouping pixels in pixel regions (PR) where buffering is shared –DUT: pixel region (behavioral level description) –2 buffering architectures under study: –fully shared buffer –shared hit time buffer + independent hit charge buffers (like ATLAS FE-I4) CMS Phase 2 Pixel Electronics meeting – 27/01/2015 6/8 Example of buffer occupancy of a 4x4 pixel region: comparison between VEPIX53 and first estimate statistical/analytical assumptions

7. Current plans CMS Phase 2 Pixel Electronics meeting – 27/01/2015 7/8 Importing external hit data from sensor / Monte Carlo simulations (ROOT or txt files) provided by both ATLAS and CMS Integration and simulation of complete pixel chip (starting from ATLAS FE-I4) In-depth architecture study –different pixel region sizes and organizations –beyond behavioral description level (synthesis on 65nm) –data formatting and compression –low power optimization Introduction of non-idealities (e.g. timewalk) Simulation of radiation effects (SEUs, fault tolerance) Implementation of automated integrated performance analysis People involved in RD53 simulation working group Elia Conti (CERN), Sara Marconi (INFN Perugia – CERN), Niloufar Alipour Tehrani (CERN), Rebecca Carney (LBNL), Tomasz Hemperek (Bonn, RD53 working group convener)

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9. 13/22 Increasing complexity of Systems on Chip (SoC) and time-to-market pressures Need to design at system level –avoid gate-level semantics –manage complexity –speed up simulation –support HW/SW co-design Increased effort for verification –constrained-random stimulus –functional coverage –layered testbench –reusability and reconfigurability High level development tools and criticalities of application (I) [Srouji] CMS Phase 2 Pixel Electronics meeting – 27/01/2015

10. 14/22 High level development tools and criticalities of application (II) High level description languages –Simulink, C++ (very high level models) –SystemC (Transaction Level Modeling (TLM)) [IEEE 1666-2011] –SystemVerilog [IEEE 1800-2012] Design –conciseness of expression –C/C++ data types –support of multiple description levels –gate-level –Register-Transfer Level (RTL) –behavioral –TLM Verification –assertions –object-oriented programming techniques –Universal Verification Methodology (UVM) library –set of documented base classes –highly customizable reporting features [Sutherland et al., 2010; Spear, Tumbush, 2012] –adopted in industry [Yun et al., ISOCC, 2011; Yang et al., VLSI-DAT, 2014; Zhong et al., ASICON, 2013] –started being adopted in HEP as well [Poikela et al., J. Instrum., 2012; Zivkovic et al., J. Instrum., 2012] CMS Phase 2 Pixel Electronics meeting – 27/01/2015

11. 15/22 Next generation pixel readout chips for High Energy Physics experiments at the Large Hardon Collider (LHC, CERN) Goal: 5×10 -34 cm -2 s -1 luminosity ParameterRequired value Technology node65 nm Pixel size25×100 µm 2 ; 50×50 µm 2 Trigger latencyup to 20 µs Radiation tolerance10 MGy (10 years) Power consumption0.3 W/cm 2 Hit rate1–2 GHz/cm 2 Output bandwidth3.6 Gbit/s RD53 Collaboration (international) (Development of pixel readout integrated circuits for extreme rate and radiation) CHIPIX65 Project (italian) [Christiansen, Garcia-Sciveres, CERN-LHCC-2013-008] [Rossi et al., 2006] [Ballabriga et al., J. Instrum., 2013] High level development tools and criticalities of application (III) CMS Phase 2 Pixel Electronics meeting – 27/01/2015

12. 12 CMS Phase 2 Pixel Electronics meeting – 27/01/2015

13. 8/20 The VEPIX53 Verification Components – Hit generation (I) General parameters (full matrix): – Pixel chip size (z x ϕ ) –Pixel pitch –Pixel chip area –Sensor thickness Class of hits generated at each BX: 1.Single tracks –at a given angle 2.Jets –multiple clusters in a given area (seen as multiple tracks) 3.Loopers –low energy particles (seen as single track crossing at 90°) 4.Monsters –very “long” tracks 5.Noise hits –not correlated with tracks Information contained in high level hit transaction object: –time (BX - with possibly random delay to be added) – hit array (row + column of fired pixels, charge or ToT) NB: hits are generated for full matrix and are driven into a subset (DUT) interaction point sensor CMS Phase 2 Pixel Electronics meeting – 27/01/2015

14. 9/20 The VEPIX53 Verification Components – Hit generation (II) Each class of hit is parameterized: 1.Single tracks –track rate –track angle (i.e. cluster length) –level of charge sharing Interaction point Sensor Examples of generated tracks (track angle 30°, sensor thickness 100um, level 1 charge sharing and different percentage of hit pixels in charge sharing envelope) CMS Phase 2 Pixel Electronics meeting – 27/01/2015

15. RD53 Collaboration Meeting – 11/04/2013 – Elia Conti (University of Perugia/INFN Perugia) 10/20 The VEPIX53 Verification Components – Hit generation (III) Each class of hit is parameterized: 2.Jets –jet rate –tracks per jet –jet area –track parameters for each track JET

16. 11/20 The VEPIX53 Verification Components – Hit generation (IV) Each class of hit is parameterized: 3.Loopers –looper rate –level of charge sharing 4.Monsters –monster rate – monster direction (z or ϕ ) Zoom on square loopers (1x1) Monster on z direction Monster on ϕ direction CMS Phase 2 Pixel Electronics meeting – 27/01/2015

17. The VEPIX53 Verification Components – Hit monitoring 12/20 The hit subscriber is responsible of dumping/analyzing generated hits (hits are therein accumulated) It is possible to choose between different levels of detail hit env hit master sequencer hit master seq lib hit master agent hit map file hit monitor hit master driver hit subscriber hit histo- grams stati- stics file CMS Phase 2 Pixel Electronics meeting – 27/01/2015

18. RD53 Collaboration Meeting – 11/04/2013 – Elia Conti (University of Perugia/INFN Perugia) The VEPIX53 Verification Components – Conformity checks and statistics collection 13/20 Reference model: pixel chip output prediction Scoreboard: conformity checks between predicted and actual output (comparator matches/mismatches reported in log file) Lost hits subscriber: classification of lost hits (PUC busy/PR busy) Buffer subscriber: histogram of PR buffer occupancy analysis env analysis master agent analysis monitor analysis reference model analysis scoreboard hit trigger readout analysis buffer subscriber buffer occupancy output file analysis lost hits subscriber lost hits output file

19. 19 Goal of buffer occupancy study: determine most convenient PR configurations Preliminary statistical/analytical study carried out based on hypotheses on shapes of clustered hits, elaborated using only assumption on position in detector Performance of PR configurations evaluated by calculating number of memory bits in shared PR buffer Simulation results on buffer occupancy