1. EMC Models

2. March 2008 2 IC designers want to predict EMC before fabrication Models – What for ? Noise margin Switching Noise on Vdd IC designers want to predict power integrity and EMI during design cycle to avoid redesign EMC models and prediction tools have to be integrated to their design flows

3. March 2008 3 © Siemens Automotive Toulouse Most of the time, EMC measurements are performed once the equipment is built. No improvements can be done at conception phase. Predict EMC performances  IC, board, equipment optimizations However, need of non-confidential IC models (black box models) Models – What for ? Equipment designers want to predict EMC before fabrication

4. March 2008 4 Complexity Level Equipment Board Component Physical spice V, Z 10 6 R,L,C,I LEECS ICEM Dipoles 10 2 R,L,C,I 10 1 R,L,C,I 10 1 dipoles 10 0 V(f), 10 0 Z(f) x-highhighlowmedium Expo PowerSI 10 4 R,L,C,I EMC Models depends on the targeted complexity, the level of confidentiality of information. Confidentiality EMC of IC models

5. March 2008 5 Model of the package : R,L,C Transmission line Core Model of the die : internal activity (core) on-chip decoupling supply network I/O structure Core Package IC EMC of IC model The model of an IC can be derived from its physical architecture. It includes the core and package model.

6. March 2008 6 EMC of IC models Core – I/O Model Package Model Test bench ModelTest board Model EMC Model for the circuit Electrical Simulation Simulated Emission spectrum General flow to build an EMC model and predict EMC performances

7. March 2008 7 Physical Transistor level (Spice) Huge simulation Limited to analog blocks Interpolated Transistor level Difficult adaptation to usual tools Limited to 1 M devices Simple, not limited Fast & accurate Gate level Activity (Verilog) Activity estimation from data sheet Very simple, not limited Immediate, not accurate Core model Model core activity: noise source Equivalent Current generator Extraction

8. March 2008 8 Core model Model The IC using a complete power supply distribution network Chip model Package model Floorplanning, physical layout Package model Chip model Elementary cell Vdd1 Vss1 Vdd2 Vss2  Full chip switching noise analysis, mapping of voltage drop, evaluation of power integrity, crosstalk, EMI, effect of on-chip decoupling.  Very accurate but large netlists.  Too much complex to add PCB model.  Adapted for IC designer issues.

9. March 2008 9 PowerSI - Real-time voltage noise simulation (right), including on-chip decoupling capacitors, shows a more stable on-chip power supply © Sigrity http://www.sigrity.com Core model Model core activity: Tool example - PowerSI Layout Silicium voltage drop map Accurate but high level of complexity

10. March 2008 10 Core model Model The IC using double LC system Emission Level (dBµV) Frequency (MHz) Example of measurement of IC conducted emission Envelop of spectrum 1st resonance 2nd resonance

11. March 2008 11 Package model IC model Core model Model The IC using double LC system Ib Rvdd Cd Lvdd RvssLvss Cb LPackVdd LPackVss External VDD External VSS ICEM model (IEC 62014-3) Secondary resonance Primary resonance Frequency Emission level Low L,C values => High resonant frequency

12. March 2008 12 [Component] Fx45H725 [Manufacturer] Finex [Package] | variable typ min max | R_pkg 800m 500m 950m L_pkg 6nH 5.5nH 7.5nH C_pkg 8pF 4pF 10.5pF [Pin] signal model R_pin L_pin C_pin 1 /1OE in1 921m 7.25nH 10.1pF 2 1Y1 out 1 916m 7.17nH 9.94pF … [Component] Fx45H725 [Manufacturer] Finex [Package] | variable typ min max | R_pkg 800m 500m 950m L_pkg 6nH 5.5nH 7.5nH C_pkg 8pF 4pF 10.5pF [Pin] signal model R_pin L_pin C_pin 1 /1OE in1 921m 7.25nH 10.1pF 2 1Y1 out 1 916m 7.17nH 9.94pF … IO Model IBIS: Input Buffer I/O specification IBIS file  I/O switching noise prediction  I/O immunity prediction Very important for : Input driver I(V) characteristics Output driver I(V) characteristics

13. EMC Guidelines

14. March 2008 14 1.Golden Rules for low emission Power supply routing strategy Decoupling capacitance Reduction of core noise Reduction of IO noise 2. Golden Rules for low susceptibility Decoupling capacitance Isolation of Noisy blocks Reduce desynchronization issues Improve noise immunity of IOs Summary

15. March 2008 15 Lead: L=0.6nH/mm Bonding: L=1nH/mm Golden Rules for Low Emission Inductance is a major source of resonance Each conductor acts as an inductance Ground plane modifies inductance value (worst case is far from ground) A) Use shortest interconnection to reduce the serial inductance Rule 1: Power supply routing strategy Reducing inductance decreases SSN !!

16. March 2008 16 A) Use shortest interconnection to reduce the serial inductance Leadframe package: L up to 10nH Rule 1: Power supply routing strategy PCB Long leads Die of the IC Close from ground bonding Die of the IC Short leads balls Flip chip package: L up to 3nH Far from ground Requirements for high speed microprocessors : L < 50 pH ! Golden Rules for Low Emission

17. March 2008 17 Correct Fail 9 I/O ports Golden Rules for Low Emission B) Place enough supply pairs: Use One pair (V DD /V SS ) for 10 IOs Rule 1: Power supply routing strategy

18. March 2008 18 Current density simulation Golden Rules for Low Emission C) Place supply pairs close to noisy blocks Rule 1: Power supply routing strategy Layout view Digital core Memory PLL V DD / V SS

19. March 2008 19 to increase decoupling capacitance that reduces fluctuations to reduce current loops that provoke magnetic field Golden Rules for Low Emission D) Place VSS and VDD pins as close as possible Rule 1: Power supply routing strategy Current loop EM field Added contributions currents Die Lead current EM wave current EM wave Reduced contributions

20. March 2008 20 Case 1 : Infineon Tricore Case 2 : virtex II Golden Rules for Low Emission Rule 1: Power supply routing strategy Worst case not enough supply pairs, bad distribution & dissymmetry Not ideal Not enough supply for IOs : (core emission is lower than IO one) Case study 2:

21. March 2008 21 courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.comwww.sigcon.com Golden Rules for Low Emission 2 FPGA, same power supply, same IO drive, same characteristics Supply strategy very different ! Case study 2: Rule 1: Power supply routing strategy More Supply pairs for IOs Better distribution More Supply pairs for IOs Better distribution

22. March 2008 22 courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.comwww.sigcon.com Golden Rules for Low Emission Case 1: low emission due to a large number of supply pairs well distributed Case 2: higher emission level (5 times higher) Rule 1: Power supply routing strategy

23. March 2008 23 Parasitic emission (dBµV) -10 0 10 20 30 40 50 60 70 80 1101001000 Frequency (MHz) Customer’s specification No decoupling to keep the current flow internal Local energy tank to reduce the supply voltage swing Golden Rules for Low Emission Rule 2: Add decoupling capacitance 10 – 15 dB Volt time Internal voltage drop 10-100 nF decoupling time Efficient on one decade

24. March 2008 24 Golden Rules for Low Emission Rule 2: Add decoupling capacitance Voltage regulator Power supply Ground On chip interconnections Vdd Vss PCB planes Electrolytic bulk capacitor 1 µF – 10 mF HF ceramic capacitor 100 nF – 1 nF Power distribution network DC – 1 KHz 1 KHz – 1 MHz 1 MHz – 100 MHz < 100 MHz Z Vdd - Vss Frequency Target impedance Zt (0.25 mΩ) Power distribution network design : Freq range Ferrite bead

25. March 2008 25 Golden Rules for Low Emission Rule 2: Add decoupling capacitance On chip decoupling capacitance versus technology and complexity: Devices on chip Intrinsic on-chip supply capacitance 100K1M10M 10pF 100pF 1.0nF 10nF 100M1G 100nF 0.35µm 0.18µm 90nm 65nm Example: in 65nm technology, for a 200 Million devices on chip the intrinsic capacitance is 10nF

26. March 2008 26 Golden Rules for Low Emission Rule 3: Reduce core noise Reduce operating supply voltage Reduce operating frequency Reduce peak current by optimizing IC activity, using distributed clock buffers, turning off unused circuitry, avoiding large loads, creating several operation mode

27. March 2008 27 Golden Rules for Low Emission Rule 3: Reduce core noise Clock in Add a controlled jitter on clock signal to spread the noise spectrum T Pseudorandom noise f P +/-Δf Clock out T+/-Δt Spread spectrum frequency modulation 1/T specification f

28. March 2008 28 Golden Rules for Low Emission Rule 3: Reduce core noise Asynchronous design spreads noise on all spectrum (10 dBµV reduction) data request acknowledgment Asynchronous block data clock Synchronous block 1/T specification f

29. March 2008 29 Golden Rules for Low Emission Rule 4: Reduce I/O noise Minimize the number of simultaneous switching lines (bus coding) Reduce di/dt of I/O by controlling slew rate and drive f SR Emission level T r1 T r2 1/T r1 1/T r2

30. March 2008 30 Work done at Eseo France (Ali ALAELDINE) Immunity level (dBm) Frequency Golden Rules for Low susceptibility Rule 1: Decoupling capacitance is also good for immunity No rules to reduce susceptibility Substrate isolation Decoupling capacitance DPI aggression of a digital core Reuse of low emission design rules for susceptibility Efficiency of on-chip decoupling combined with resistive supply path DPI aggression of a digital core Reuse of low emission design rules for susceptibility Efficiency of on-chip decoupling combined with resistive supply path

31. March 2008 31 Analog Standard cells Noisy blocks Far from noisy blocks Bulk isolation Separate supply Why ? To reduce the propagation of switching noise inside the chip To reduce the disturbance of sensitive blocks by noisy blocks (auto-susceptibility) How ? by separate voltage supply by substrate isolation by increasing separation between sensitive blocks By reducing crosstalk and parasitic coupling at package level Golden Rules for Low susceptibility Rule 2: Isolate Noisy blocks

32. March 2008 32 Golden Rules for Low susceptibility Rule 3: Reduce desynchronization issues Work done at INSA Toulouse/TIMA Grenoble (Fraiddy BOUESSE) Synchronous design are sensitive to propagation delay variations due to jitter (dynamic errors) Improve delay margin to reduce desynchronization failures in synchronous design Asynchronous logic design is less sensitive to delay compared to synchronous design 15 dB

33. March 2008 33 Golden Rules for Low susceptibility Rule 4: Improve noise immunity of IOs Add Schmitt trigger on digital input buffer Use differential structures for analog and digital IO to reject common mode noise Schmitt trigger 2 dB

34. Conclusion / Future of EMC

35. March 2008 35 Future of EMC Scaling leads to an increase of transient currents => EMI and SSN problems get worse 0.5 µm 0.35 µm 0.25 µm0.18 µm 0.13 µm90 nm 65 nm45 nm 0 10 20 30 40 50 60 Current Peak (A/mm²) Technology 32 nm

36. March 2008 36 0 20 40 60 80 100 10MHz100MHz1GHz Emission dBµV 10GHz 16 bits 32 bits System on chip New frequency band (1-10GHz) Frequency Towards complex systems, system on chip, system on package => Increase of emission level in a new frequency band (critical) Critical frequency bands Future of EMC

37. March 2008 37 19952000200520102015 0.1V 1V 10V Supply voltage Year 0.25  m 0.18  m0.13  m 90nm 65nm 45nm 32nm External voltage Internal voltage Noise margin or static margin 18 nm 22 nm Less noise margin : => 100mV in 2015 !!!! Future of EMC

38. March 2008 38 Most of EMC measurement methods are limited to 1 GHz. Future of EMC How characterizing accurately emission and susceptibility of ICs up to 10 GHz? IEC 61967-2 (TEM : 1GHz) IEC 61967-3/6 (Near field scan, 5GHz) IEC 61967-4 (1/150 ohm, 1 GHz) IEC 62132-2 (BCI, 1 GHz) IEC 61967-5 (WBFC, 1 GHz) IEC 61967-7 (Mode Stirred Chamber: 18 GHz) IEC 61967-2 (GTEM 18 GHz) IEC 62132-3 (DPI, 1 GHz)

39. March 2008 39 Models become more and more complex Future of EMC Chip stacking Flip-chip Substrate Passive devices V dd V ss resonance Crosstalk via Radiation System-In- Package Circuits more complex (System-on-chip, System-in-package) Power distribution networks become larger, more and more IOs More and more parasitic coupling paths (substrate coupling, package coupling) Modeling at high frequency ? How ensure accuracy and efficiency ?

40. March 2008 40 Developing new design guidelines Future of EMC Customers requirements are more and more constraining Off-chip decoupling capacitor are limited to several hundred MHz New technologies require less and less power distribution network impedance Need of efficient techniques to reduce emission and improve immunity to RFI

41. March 2008 41 Conclusion With technology scale down, ICs become more sensitive and emissive. EMC of ICs has become a major concerns for ICs suppliers Standardization groups are working on EMC characterization method (need to address high frequency) Needs for simulation models and tools to predict ICs EMC performances before fabrication New EMC oriented design rules and techniques have to be developed to ensure future ICs EMC compliance

42. March 2008 42 Books www.springeronline.comwww.ic-emc.org Tools www.emccompo.org Workshops Standards www.iec.ch IEC 61967, 2001, Integrated Circuits emissions IEC 62132, 2003, integrated circuits immunity IEC 62014-3, 2003, Integrated Circuit Model Références