1. LZRW3 Decompressor dual semester project Part A Mid Presentation Students: Peleg Rosen Tal Czeizler Advisors: Moshe Porian Netanel Yamin 22.6.2014

2. Presentation Content Project Goals Project Requirements Algorithm Overview Project Top Block Diagram Decompression Core Top View Decompression Core Design and Data Flow Stages Overview Problems and Solutions Project Schedule and Gantt

3. Project Goals

4. Implementation of LZRW3 data decompression core.

5. Implementation of a verification environment. Project Goals

6. Project Requirements

7. Part A: Core Requirements: – Process data at the speed of 1 Gbps. – Support data blocks with output of 2KB – 32KB. – Relay only on the FPGA’s internal memory. – VHDL Implementation.

8. Part A: Core Requirements: – Process data at the speed of 1 Gbps. – Support data blocks with output of 2KB – 32KB. – Relay only on the FPGA’s internal memory. – VHDL Implementation. Full simulation environment (golden model and checkers). Project Requirements

9. Part A: Core Requirements: – Process data at the speed of 1 Gbps. – Support data blocks with output of 2KB – 32KB. – Relay only on the FPGA’s internal memory. – VHDL Implementation. Full simulation environment (golden model and checkers). Part B: Synthesis & implementation of FPGA device (Xilinx Virtex-5). Project Requirements

10. Part A: Core Requirements: – Process data at the speed of 1 Gbps. – Support data blocks with output of 2KB – 32KB. – Relay only on the FPGA’s internal memory. – VHDL Implementation. Full simulation environment (golden model and checkers). Part B: Synthesis & implementation of FPGA device (Xilinx Virtex-5). GUI implementation in VisualStudio. Project Requirements

11. Output item (Copy item): [slot address, length ] In this case Output item = [, ] BABDACABDBCAA 2 1 3 0 3 LZRW3 compression algorithm Hash Function Hash Table ABD Slot address 1 45 6 BAB 0 ABD Slot address Send every 3 literals to the hash function Put offset in the hash table If the slot is occupied and the literals match - make copy item 6

12. Structure Algorithm Overview

13. Structure File header (8 byte) Algorithm Overview

14. Structure File header (8 byte) Groups: Algorithm Overview

15. Structure File header (8 byte) Groups: - control bytes (2 bytes) Algorithm Overview

16. Structure File header (8 byte) Groups: - control bytes (2 bytes) - data bytes (16 - 32 bytes) * The last group might be smaller Algorithm Overview

17. File header Decode the header to determine the file size and whether it is compressed or not. Algorithm Overview

18. Control bytes Decode control bytes to determine the position and type of the items in the group, and where the next control bytes are. Algorithm Overview

19. Literal items Write as is to output file. Algorithm Overview

20. Literal items Write as is to output file. Algorithm Overview

21. Literal items Write as is to output file. Algorithm Overview

22. Copy items Decode to determine the offset and length of a literal sequence to be copied to the output file. Algorithm Overview

23. Copy items Decode to determine the offset and length of a literal sequence to be copied to the output file. Algorithm Overview

24. Copy items Decode to determine the offset and length of a literal sequence. Write from the output memory to itself accordingly. Algorithm Overview

25. Project Top Block Diagram LZRW3 DECOMPRESSION CORE

26. Decompression Core Top view DECOMPRESSION CORE

27. Decompression Core Design and Data Flow

28. Stages Overview – Core Management Unit

29. Core Management Unit Goals: To communicate with the core's periphery. To receive the input data and parse it. To transmit the appropriate control signals to the next stages. Method: The unit starts with ‘clear’ mode, which initializes the core. The following 10 clock cycles are dedicated to Header and Control Bytes decoding. From this point on, the unit determines the Mode and sets the appropriate controls according to the current byte and the previous 4 bytes.

30. Core Management Unit – Mode selection

31. Core Management Unit – Outputs

32. Stages Overview – 5 Bytes Buffer BUSY

33. New byte (8) Mid byte (8) Old byte (8) Older byte (8) Oldest byte (8) Five Bytes Buffer New byte (8) New Byte Register Mid Byte Register Old Byte Register Older Byte Register Oldest Byte Register

34. Stages Overview – Hash Function BUSY

35. Stages Overview – Hash Function

36. #3 Hash Function Stage TABLE INDEX = (((40543*(((*(PTR)) >4) & 0xFFF) PTR pointes to the first byte. TABLE INDEX range: 0 to 4095.

37. Stages Overview – Hash Table Stage

38. Block Overview – Write Address Counter

39. Write Address Counter According to Mode signal: For Literal items increments by 1. For Copy items increments by Length. Else, doesn’t increment.

40. Block Overview – Hash Table

41. Hash Table 16 bits 4096 rows Write Address Counter Offset in Read Index (12) Offset out Write Index (12) From Hash Func From Core Mgmt 5 bits Memory number 11 bits Memory address Hash Table Select

42. Hash Table – Default String 16 bits 4096 rows 5 bits Memory number 11 bits Memory address The Default String The LZRW3 algorithm dictates that the string “123456789012345678” is set as default.

43. Hash Table – Default String 16 bits 4096 rows 5 bits Memory number 11 bits Memory address The Default String The LZRW3 algorithm dictates that the string “123456789012345678” is set as default. Meaning, when a sequence starting “123..” is received, a copy item is created, even if it is the first time the sequence appears.

44. Hash Table – Default String 16 bits 4096 rows 5 bits Memory number 11 bits Memory address 00000000000000001264 The Default String The LZRW3 algorithm dictates that the string “123456789012345678” is set as default. Meaning, when a sequence starting “123..” is received, a copy item is created, even if it is the first time the sequence appears. The index ‘1264’ is initialized with zeroes, which stand for the default string.

45. Hash Table – Default String 16 bits 4096 rows 5 bits Memory number 11 bits Memory address 00000000000000001264 The Default String The LZRW3 algorithm dictates that the string “123456789012345678” is set as default. Meaning, when a sequence starting “123..” is received, a copy item is created, even if it is the first time the sequence appears. The index ‘1264’ is initialized with zeroes, which stand for the default string.

46. Block Overview – First 2 Bytes

47. Why is First 2 Bytes needed?

48. In the original file: ABCXYZABC In the compressed file: ABCXYZC1C2

49. Why is First 2 Bytes needed? In the original file: ABCXYZABC In the compressed file: ABCXYZC1C2 If we wish to keep our Hash Table identical to the Hash Table of the compressor, we must somehow fetch AB instead of C1C2.

50. First Two Bytes 16 bits 4096 rows Old byte & Mid byte Bypass Read Index (12) Two bytes out Write Index (12) From Hash Func From Core Mgmt 8 bits First byte 8 bits Second byte Hash Table Select

51. Block Overview – First 2 Bytes C1 X Y Z X Y C2 Z BA

52. Block Overview – First 2 Bytes C1 X Y Z X Y C2 Z BA

53. Block Overview – First 2 Bytes C1 X Y Z X Y C2 Z X Y Z Y Z C1 BA INDEX

54. Block Overview – First 2 Bytes C1 X Y Z X Y C2 Z X Y Z Y Z C1 INDEX BA

55. Block Overview – First 2 Bytes C1 X Y Z X Y C2 Z X Y Z Y Z C1 INDEX B A

56. Block Overview – First 2 Bytes X Y Z C2 Y X Z X Y Z INDEX Y Z C1 INDEX B A

57. Block Overview – First 2 Bytes X Y Z C2 Y X Z INDEX Y Z C1 INDEX B A

58. Block Overview – First 2 Bytes X Y Z C2 Y X B A INDEX X Y Z Y Z C1 A

59. Stages Overview – Address Manager

61. Stages Overview – Output Memory

62. COPY MODE 3 2 - 25 1 - 7 2 - 7 3 - 7 3 - 25 4 - 25 DATA 2 DATA 1 DATA 3

63. COPY MODE 3 2 - 25 1 - 7 2 - 7 3 - 7 3 - 25 4 - 25 DATA 2 DATA 1 DATA 3

64. COPY MODE 3 2 - 25 1 - 7 2 - 7 3 - 7 3 - 25 4 - 25 DATA 2 DATA 1 DATA 3

65. COPY MODE 3 1 - 7 2 - 7 3 - 7 2 - 25 3 - 25 READ ENABLE WRITE ENABLE READ ENABLE 1 2 DATA 2 DATA 1 DATA 3

66. COPY MODE 3 1 - 7 2 - 7 3 - 7 2 - 25 3 - 25 READ ENABLE WRITE ENABLE READ ENABLE 1 2 DATA 2 DATA 1 DATA 3

67. 1 - 7 2 - 7 3 - 7 2 - 25 3 - 25 READ ENABLE WRITE ENABLE READ ENABLE 1 2 DATA 2 DATA 1 DATA 3

68. 2 - 25 3 - 25 WRITE ENABLE DATA 2 DATA 1 DATA 3

69. Timing Considerations The project requirements dictates clock frequency of 125 MHz.

70. Timing Considerations The project requirements dictates clock frequency of 125 MHz. Our concern was that the memory stage’s muxes will limit the frequency.

71. Timing Considerations The project requirements dictates clock frequency of 125 MHz. Our concern was that the memory stage’s muxes will limit the frequency. After writing the VHDL code for the memory stage we synthesized it and ran a timing analysis, which provided the following result:

72. Timing Considerations The project requirements dictates clock frequency of 125 MHz. Our concern was that the memory stage’s muxes will limit the frequency. After writing the VHDL code for the memory stage we synthesized it and ran a timing analysis, which provided the following result: Conclusion: The timing requirements will be met.

73. Primary vs Final Design 4 Kbyte FIFO Hash Function Header Decoder Control Bytes Decoder Copy Item Decoder Hash Table Write Address Counter Copy Counter Output Memory 32 Kbyte 3 Byte 1 Byte Controller Data in Index 12 Bit 4 Bit Index Length Offset in Offset out Data in Read Address From Input Block Data out Fetch stage Decode stage Calc Address stage Output Memory stage 1 Byte 3 Byte buffer Address Manager Write address Read address Write Address To Output Block

74. Problems and Solutions Problem #1: Preforming a copy procedure

75. Problems and Solutions Problem #1: Preforming a copy procedure In the initial design: only 1 output memory.

76. Problems and Solutions Problem #1: Preforming a copy procedure In the initial design: only 1 output memory. The problems:

77. Problems and Solutions Problem #1: Preforming a copy procedure In the initial design: only 1 output memory. The problems: - Wasting copy length clock cycles in order to copy item.

78. Problems and Solutions Problem #1: Preforming a copy procedure In the initial design: only 1 output memory. The problems: - Wasting copy length clock cycles in order to copy item. - Must stop the pipe and store the incoming data in a FIFO located at the core’s beginning while copying.

79. Problems and Solutions Problem #1: Preforming a copy procedure In the initial design: only 1 output memory. The problems: - Wasting copy length clock cycles in order to copy item. - Must stop the pipe and store the incoming data in a FIFO located at the core’s beginning while copying. - Demands a very complicated controller.

80. Problems and Solutions Problem #1: Preforming a copy procedure In the initial design: only 1 output memory. The problems: - Wasting copy length clock cycles in order to copy item. - Must stop the pipe and store the incoming data in a FIFO located at the core’s beginning while copying. - Demands a very complicated controller. The solution:

81. Problems and Solutions Problem #1: Preforming a copy procedure In the initial design: only 1 output memory. The problems: - Wasting copy length clock cycles in order to copy item. - Must stop the pipe and store the incoming data in a FIFO located at the core’s beginning while copying. - Demands a very complicated controller. The solution: 18 different memory blocks, which enable us to preform every copy in 2 clock cycles: 1 for reading the data from all the required memories, and the second for writing the data back to the right memories. No dependency on copy length!

82. Problems and Solutions Problem #2: Ignoring the Control Bytes

83. Problems and Solutions Problem #2: Ignoring the Control Bytes In the initial design: 3 bytes buffer.

84. Problems and Solutions Problem #2: Ignoring the Control Bytes In the initial design: 3 bytes buffer. The problem:

85. Problems and Solutions Problem #2: Ignoring the Control Bytes In the initial design: 3 bytes buffer. The problem: the Control Bytes are needed for the core management unit to operate correctly, but must be ignored in the data flow (they mustn't be written in the hash table, and we need to remember the preceding items). The problem was how to ignore them without losing data.

86. Problems and Solutions Problem #2: Ignoring the Control Bytes In the initial design: 3 bytes buffer. The problem: the Control Bytes are needed for the core management unit to operate correctly, but must be ignored in the data flow (they mustn't be written in the hash table, and we need to remember the preceding items). The problem was how to ignore them without losing data. The solution:

87. Problems and Solutions Problem #2: Ignoring the Control Bytes In the initial design: 3 bytes buffer. The problem: the Control Bytes are needed for the core management unit to operate correctly, but must be ignored in the data flow (they mustn't be written in the hash table, and we need to remember the preceding items). The problem was how to ignore them without losing data. The solution: Enlarging the buffer from 3 bytes to 5 bytes which enables us to remember the items that preceded the Control Bytes. This done, we can select the preceding items and 'bypass' the Control Bytes with the 5 bytes buffer mux.

88. Problems and Solutions Problem #3: Maintaining the Hash Table Correctly

89. Problems and Solutions Problem #3: Maintaining the Hash Table Correctly In the initial design: No First 2 Bytes memory.

90. Problems and Solutions Problem #3: Maintaining the Hash Table Correctly In the initial design: No First 2 Bytes memory. The problem:

91. Problems and Solutions Problem #3: Maintaining the Hash Table Correctly In the initial design: No First 2 Bytes memory. The problem: Before acting on a copy item, the first two bytes of the literal sequence represented by the copy should be concatenated with the previous literal items.

92. Problems and Solutions Problem #3: Maintaining the Hash Table Correctly In the initial design: No First 2 Bytes memory. The problem: Before acting on a copy item, the first two bytes of the literal sequence represented by the copy should be concatenated with the previous literal items. The solution:

93. Problems and Solutions Problem #3: Maintaining the Hash Table Correctly In the initial design: No First 2 Bytes memory. The problem: Before acting on a copy item, the first two bytes of the literal sequence represented by the copy should be concatenated with the previous literal items. The solution: Maintaining the First 2 bytes memory, which holds the first 2 bytes of each literal sequence whose offset is written to the hash table. This way, concatenation is possible by extracting the necessary bytes from the first 2 bytes memory.

94. New Problem Problem #4: Copy adjacent to the sequence it points to

95. New Problem Problem #4: Copy adjacent to the sequence it points to The problem:

96. New Problem Problem #4: Copy adjacent to the sequence it points to The problem: When trying to concatenate the first 2 bytes of a copy, there is a problem if the copy item arrives straight after the literal sequence that created it. The first 2 bytes are not yet stored, thus cannot be retrieved.

97. New Problem Problem #4: Copy adjacent to the sequence it points to The problem: When trying to concatenate the first 2 bytes of a copy, there is a problem if the copy item arrives straight after the literal sequence that created it. The first 2 bytes are not yet stored, thus cannot be retrieved. The proposed solution:

98. New Problem Problem #4: Copy adjacent to the sequence it points to The problem: When trying to concatenate the first 2 bytes of a copy, there is a problem if the copy item arrives straight after the literal sequence that created it. The first 2 bytes are not yet stored, thus cannot be retrieved. The proposed solution: Comparator, which determines if the index of the copy item is the last index written to in the Hash Table. If so, the relevant data is bypassed.

99. DateGoals 21/3/2014 – 5/4/2014Project Characterization & Algorithm interpreting 6/4/2014Characterization Presentation 7/4/2014 – 2/6/2014Full Characterization of all blocks 3/6/2014 – 21/6/2014 System blocks VHDL Design 22/6/2014Mid presentation 23/6/2014 – 25/7/2014Work on project paused for exams Project Schedule 1/2

100. DateGoals 30/7/2014 – 4/9/2014VHDL design Cont. 21/9/2014 – 20/10/2014Building a simulation environment 21/10/2014 – 21/11/2014Simulation run & debug 22/11/2014Part A - Final presentation 23/11/2014 – 10/12/2014FPGA synthesis & implementation 11/12/2014 – 25/12/2015GUI implementation 26/12/2014 – 24/1/2015Tests & debug 25/1/2015Final project presentation Project Schedule 2/2

101. Weeks: 0 - 5 6 – 12 13 – 19 20 - 26 27 - 32 Characterization & interpretation Characterization presentation Blocks characterization VHDL blocks implementation Mid presentation Exams VHDL Cont. Building Sim Env Part A - Final pres. Sim & Debug FPGA synthesis GUI implementation Tests & debug Writing portfolio Final presentation …….............………...…………… ….…….……………………………………………………….…............ Project Gantt ……...….…….…………………………………… 3 3 3 3 2 2 2 2 2 2 2 2 4 4 4 4 2 2 8 8 4 4