1. November, 2005 IECON 2005 1 Optimized design of a back-to-back NPC converter to be used as interface of renewable energies Emilio J. Bueno 1), Santiago Cobreces 2), Francisco J. Rodríguez 3), Álvaro Hernández 4), Felipe Espinosa 5), Raúl Mateos 6), Juan C. García 7), Félix López 8) 1,2,3,4,5,6,7) Department of Electronics, Alcalá University 8) SEDECAL CONTROL 28871 Alcalá de Henares (Madrid) SPAIN28110 Algete (Madrid) SPAIN emilio@depeca.uah.esFLopez@sedecal.com

2. November, 2005 IECON 2005 2 Contents 1.Introduction. 2.Power Electronics System. 3.Control Electronics System. 4.Practical results. 5.Summary.

3. November, 2005 IECON 2005 3 Disturbances … Problems to solve in the connection of VSCs to the grid (1/2) Distribution line Motor VSC1 VSC2 3*L 1 3*L 2 3*C o C DC P N Line impedance from the converter towards the grid:  PWM commutations. Can be reduced using a LCL-filter and a mutilevel converter.  Temporal drifts of the filter components.  Inductances saturation. from the grid towards the converter:  Unknown line impedance (weak grid).  Line voltage harmonics.  Permanent unbalanced line voltages.  Temporal unbalanced line voltages (dips).

4. November, 2005 IECON 2005 4 Problems to solve in the connection of VSCs to the grid (2/2) Motor VSC1 VSC2 3*L 1 3*L 2 3*C o C DC P N Distribution line Fault Line impedance Hardware:  Rotor energy storage.  Braking chopper.  DC-bus energy storage.  Overcurrent.  Active crowbar. Software:  Generation of new reference currents Solutions to avoid the converter switch-off Response under voltage dip of VSCs connected to the grid in variable speed wind turbines  Under fault P g < P W.  It produces an energy excess that should be dissipated or storage.

5. November, 2005 IECON 2005 5 “CONDOR” project (1/2)  CONDOR: “Double converter based on multilevel inverters designed for recovering energy and minimizing electromagnetic emissions”.  Financed by the Spanish Science and Technology Ministry (DPI2002-04555-C04).  Duration: December, 2002 – December, 2005.  Researching groups: University of Alcalá (Coordinator), University of Carlos III, University of Valencia and Institute for Electrical Technology of Valencia.  Collaborating companies: SEDECAL CONTROL. N n AC Motor VSC1 VSC2 S a2 S a1 S a2 S a1 S b2 S b1 S b2 S b1 S c2 S c1 S c2 S a2 S a1 S a2 S a1 S b2 S b1 S b2 S b1 S c2 S c1 S c2 S c1 3*L 1 3*L 2 3*C o C DC2 NP P C DC1 D a2 D a1 D b2 D b1 D c2 D c1 D a2 D a1 D b2 D b1 D c2 D c1 eaea ebeb ecec PCC S c1

6. November, 2005 IECON 2005 6 “CONDOR” project (2/2) AC motor VSC1VSC2 3*L 1 3*L 2 3*C o C DC2 NP P N C DC1 eaea ebeb ecec PCC n Auxiliar breaker Main breaker Auxiliar rectifier Power Electronics System ADCs Measurements of grid filter variables ADCs Measurements of DC-bus variables ADCs Measurements of motor variables PWM VSC 1PWM VSC 2 FPGA SPARTAN 2E DSP TMS6713 VSC 1 ControlVSC 2 Control Communication card Interface card between the Coprocessor Module – Power Electronics System Coprocessor Module References Control Electronics System References

7. November, 2005 IECON 2005 7 Objectives  This work presents the construction of the Power Electronics System, the converter limitations to compensate unbalanced dips, and the designs of grid filter components and DC-bus capacitors.  In this work the grid filter is the LCL and the analytical equations for the components are obtained to verify the ICE 61000-3-4 standard.  As for the DC-bus capacitors, the analytical equations for the ripples in u DC due to i DC and i NP are obtained. From these equations, the DC-bus capacitors are calculated.  With respect to the Control Electronics System, the chosen structure and the task distribution between the system processors are presented.

8. November, 2005 IECON 2005 8 Contents 1.Introduction. 2.Power Electronics System. 3.Control Electronics System. 4.Practical results. 5.Summary.

9. November, 2005 IECON 2005 9 Power electronics specifications and assembly Specifications of the utility grid and the converter

10. November, 2005 IECON 2005 10 Converter limitations to compensate unbalanced dips  The maximum peak phase current to compensate the unbalanced voltage dips and with zero phase jump can be calculated approximately as:  The system must be oversized to compensate voltage dips to nominal power. The elements that limit this current are mainly the grid filter inductances and the IGBT’s.  If the excess energy is not stored or dissipated the DC-bus voltage increases. The elements that determine the DC-bus voltage limitations are the IGBTs (maximum direct collector emitter voltage) and the DC-bus capacitors (nominal voltage).

11. November, 2005 IECON 2005 11 Grid filter design Filter limitations  Resonance frequency.  Inductance. The total value of the inductances should not be bigger than 10% of L base.  Capacitor. i1 in function of Co is: The design expressions are  C o is the 5% of C base.  Chosen values are  L1=0.5mH/175Arms.  L2=0.25mH/150Arms.  Co=100μF/400Vrms.

12. November, 2005 IECON 2005 12 Calculation of the DC-bus capacitors Simplified diagram of a back-to-back converter based on two NPC’s Ripple due to i DC Ripple due to i NP

13. November, 2005 IECON 2005 13 Contents 1.Introduction. 2.Power Electronics System. 3.Control Electronics System. 4.Practical results. 5.Summary.

14. November, 2005 IECON 2005 14 Control electronics system (1/3)

15. November, 2005 IECON 2005 15 Control electronics system (2/3) Control Electronics System ADCs Measurements of grid filter variables ADCs Measurements of DC- bus variables ADCs Measurements of motor variables PWM VSC 1PWM VSC 2 FPGA SPARTAN 2E DSP TMS6713 VSC 1 ControlVSC 2 Control Communication card Interface card between the Coprocessor Module – Power Electronics System Coprocessor Module References

16. November, 2005 IECON 2005 16 Control electronics system (2/2)

17. November, 2005 IECON 2005 17 Contents 1.Introduction. 2.Power Electronics System. 3.Control Electronics System. 4.Practical results. 5.Summary.

18. November, 2005 IECON 2005 18 “CONDOR” project (2/2)

19. November, 2005 IECON 2005 19 Some converter waveforms VSC1 working as non controlled rectifier and VCS2 driving to induction machine Ripple due to i NP Ripple due to i DC

20. November, 2005 IECON 2005 20 Controller programming AreasCode Size CountIncl. Total Incl. Max. Incl. Min. Inc. Aver. main()184144157200 init_system()328141384800 c_int(5)47255397135731071127220 acquisition_data()132455121487223021962208 reference_PWM()7805540578754607737 spll_pi()7205542517778772773 dsc()14405550961983924926 currentcontroller()364855107030200518451946 dcbuscontroller()5485513864256252 c_int(4)22011393700 system_protection()14417005 Data acquisition Start main() and init_system() t(k)=k·T S =k ·200μs No Output controller reference_PWM() PI SPLL spll_pi() DSC dsc() Current controller currentcontroller() DC_bus controller dcbuscontroller() Any fault? System protection system_protection() Stop Any hardware fault? Yes → c_int(4) Yes Yes → c_int(5) No + + acquisition_data() c_int(5) Control algorithm  TMS320C6713 DSP is operating at 225MHz.  Cycle clock is 4.44ns.  Sampling time is 200μs  The execution average time of the Control algorithm is 32μs.

21. November, 2005 IECON 2005 21 SPLL practical results and publications e gan e gbn Measurements of grid phase voltages Acquisition of grid phase voltages dq components

22. November, 2005 IECON 2005 22 Contents 1.Introduction. 2.Power Electronics System. 3.Control Electronics System. 4.Practical results. 5.Summary.

23. November, 2005 IECON 2005 23 Summary  A back-to-back NPC three-level converter of 100KVA has been designed, validated by simulation and tested in a real converter.  In the “Power Electronics System”: (1) the converter limitations to compensate voltage dips have been analysed; (2) a method for designing the grid filter components has been proposed; and (3) the factors that determine the DC-bus capacitor values have been analysed.  With respect to the “Control Electronics System”, the chosen structure and the task distribution between the two processors have been presented.

24. November, 2005 IECON 2005 24 Thank you for your attention!!! Emilio J. Bueno 1), Santiago Cobreces 2), Francisco J. Rodríguez 3), Álvaro Hernández 4), Felipe Espinosa 5), Raúl Mateos 6), Juan C. García 7), Félix López 8) 1,2,3,4,5,6,7) Department of Electronics, Alcalá University 8) SEDECAL CONTROL 28871 Alcalá de Henares (Madrid) SPAIN28110 Algete (Madrid) SPAIN emilio@depeca.uah.esFLopez@sedecal.com Acknowledgment: This work has been financed by the Spanish administration (CICYT: DPI2002-04555-C04-04).