2. ©Richard L. Goldman 1 IRQ Interrupt Requests (Static Presentation) ©Richard L. Goldman April 25, 2002

3. ©Richard L. Goldman 2 Hardware Interrupts Hardware interrupts are signals from different devices in the computer. The interrupts are sent along dedicated traces to the CPU. When the CPU receives an interrupt is stops the job that it is doing and saves it in a memory stack. The CPU then processes the job associated with the interrupt. The interrupts and other CPU job are processed in order according to an established priority. Several jobs may be stored in memory stacks while higher priority jobs are being run.

4. ©Richard L. Goldman 3 IRQ Assignments IRQ # Assignment IRQ # Assignment 0System Timer8Real-time Clock 1Keyboard9NIC 22 nd IRQ Controller10USB 3Com 2 & 4 (Int. Modem)11SCSI 4Com 1 & 312System Mouse 5LPT 2 or Sound Card13Math Coprocessor 6Floppy Disk14Primary IDE (C: Hard Drive) 7LPT 1 (Printer)15Secondary IDE (CD-ROM) Set Function Standard Function Recommended Use

5. ©Richard L. Goldman 4 Sys TimerKeyboardRTCMath CP CPU 32 Bit PCI Slots 8 Bit ISA Slots 16 Bit ISA Slots USB System Mouse LPT 1 LPT 2 Parallel Ports FDD Serial Ports Com 2Com 1 0123456701234567 Interrupt Controller 8259 (#1) INT 8 9 10 11 12 13 14 15 Interrupt Controller 8259 (#2) INT Primary Secondary IDE Channels ABCDABCD PCI Controller IRQ Steering IRQ Wiring SCSI Controller

6. ©Richard L. Goldman 5 Interrupt Dialog CPUMemoryHardware Device (modem) IRQ#3 (I need attention) Who is assigned IRQ#3 ? IRQ#3 is the Modem at I/O address 0FEEFA I/O address 0FEEFA - ACK (modem, what do you want) INT 6 (Do my handler program #6) Get and run handler at Address 0FC2F7 Interrupt Vector Table Where is modem handler #6 stored? Modem handler #6 is at memory address 0FC2F7

7. ©Richard L. Goldman 6 IRQ Priorities IRQ # Priority Assignment IRQ # Priority Assignment 00System Timer82ARTC 11Keyboard92BNIC 2---Above 7 IRQs102CUSB 33Com 2 & 4112DSCSI 44Com 1 & 3122ESystem Mouse 55Sound or LPT 2132FMath CP 66Floppy Disk142GPrimary IDE 77LPT 1152HSecondary IDE

8. ©Richard L. Goldman 7 IRQ Assignment Review IRQ # Assignment IRQ # Assignment 0Sys Time8RTC 1KB9NIC 2---10USB 3Com 2 & 411SCSI 4Com 1 & 312Sys Mouse 5Sound / LPT 213Math CP 6FDD14P IDE 7LPT 115S IDE

9. ©Richard L. Goldman 8 IRQ Assignment Quiz IRQ # Assignment IRQ # Assignment 08 19 210 311 412 513 614 715

10. ©Richard L. Goldman 9 ISA & PCI Bus Signaling PCI interrupts use Level-sensitive Signaling Off Slot 1 Slot 2 Slot 3 Slot 4 5 VDC 4 VDC 3 VDC 2 VDC 0 VDC ISA interrupts use Edge-triggered Signaling Off On 0 VDC 5 VDC ISA interrupts must use one trace for each interrupt. Many different PCI interrupts can use the same trace. Most all PCI devices share PCI interrupt A.