1. Lecture #2 Page 1 ECE 4110– Sequential Logic Design Lecture #2 Agenda 1.Logic Design Tools Announcements 1.n/a

2. Lecture #2 Page 2 Logic Design Tools MS Visio - a generic drawing program. - industry is converging on this program for documentation. - has built in shape libraries, including analog/digital logic. - we’ll use it for this class to create clean schematics.

3. Lecture #2 Page 3 Logic Design Tools MS Visio Predefined Shapes

4. Lecture #2 Page 4 Logic Design Tools ModelSim (by Mentor Graphics) - an HDL Simulation (VHDL and Verilog) - widely used in industry - has color-coded text editing for keywords - has console for verification reporting - we’ll use for homework & before FPGA synthesis.

5. Lecture #2 Page 5 Logic Design Tools ModelSim Simulation Waveform Project Navigator Console

6. Lecture #2 Page 6 Logic Design Tools ModelSim Text Editor

7. Lecture #2 Page 7 Logic Design Tools Xilinx ISE - Integrated Software Environment (ISE) - Implementation tool - compile / simulate - synthesis - technology mapping - place and route - back annotation for post-route simulation and timing verification - can do similar simulation as in ModelSim - this is where we : - select FPGA to target - assign signal pins - set timing constraints - set placement constraints - set routing constraints - generate programming file - download file to FPGA, EEprom, or CPLD using the JTAG interface.

8. Lecture #2 Page 8 Logic Design Tools Xilinx ISE Sources Window Processes Window Edit/View Window

9. Lecture #2 Page 9 Logic Design Tools Xilinx ISE Resource Usage Pin Assignments Package View

10. Lecture #2 Page 10 Logic Design Tools Xilinx ISE HDL or Schematic Entry Routing Editor

11. Altera Quartus II Development Tool Lecture #2 Page 11

12. Example of File Menu Lecture #2 Page 12

13. New Project Wizard Lecture #2 Page 13

14. Creation of new project Lecture #2 Page 14

15. Adding files to project Lecture #2 Page 15

16. Choose device family and specific device Lecture #2 Page 16

17. Electronic Design Automation Tools Lecture #2 Page 17

18. Summary of project settings Lecture #2 Page 18

19. Quartus II display of created project Lecture #2 Page 19

20. Processing>Start Compilation Lecture #2 Page 20

21. Assignment > Pins For example, SW0,SW1 are connected on FPGA Pins N25,N26. LEDG0 is pin AE22. Lecture #2 Page 21

22. Available pins Lecture #2 Page 22

23. Programming the FPGA: Tools>Programmer Check the Program/Configure box, then click Start. Wait till the progress bar show 100% (done). Lecture #2 Page 23