1. ASIC development foreseen at IHEP/ORSAY C. de La Taille

2. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 2 Microelectronics at in2p3 Large force of microelectronics experienced engineers (~40) Expertise in detectors, connectics, chip design and test Experience in designing and building large trackers Common Cadence tools Actions : –Building blocks –Networking –poles

3. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 3 « Club 0.35 » R&D building blocks in2p3 Mission : Design of basic building blocks usable by all in2p3 labs for physics experiments Motivations –Target analog technology (0.35µm CMOS and SiGe AMS ) –Optimize ressources and competences within in2p3 –reduce developpement times –Increase visibility of in2p3 in microelectronics First results –2-3 runs /yr financed by in2p3 –Porquerolles workshop –Fruitful exchanges

4. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 4 Motivation for poles Continuous increase of chip complexity (SoC, 3D…) Importance of critical mass –Daily contacts and discussions between designers –Sharing of well proven blocks –Cross fertilization of different projects Creation of poles at in2p3 –OMEGA at Orsay –Strasbourg –Dipole Lyon-Clermont –Marseille ?

5. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 5 Possible extension for tracking Networking : club 0.13µm ? –Target common technology with CERN or other labs : IBM 0.13? Achieve a good consortium –Complementarity –Task sharing –Coordination Possible part of larger framework –European infrastructure ? Recommendation : participate to 3D effort in a coherent, coordinated and funded way.

6. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 6 HardROC Orsay Micro-Electronics Groups Associated A strong team of 10 ASIC designers… –= 20% of in2p3 designers –= 60% of department research engineers –A team with critical mass : pole created in 2007 = OMEGA –Expertise in low noise, low power high level of integration ASICs –2 designers/ project –2 projects/designer –Regular design meetings …Within an electronics department of 55 –Support for tests, mesaurements, PCBs… A steady production –1-2 large productions/year A strong on-going R&D –Building blocks SiGe 0.35µm SkiROC MAROC 2 SPIROC

7. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 7 Orsay micro-electronics team

8. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 8 Recent chips Several chips developped for ATLAS LAr, OPERA, LHCb, CALICE in BiCMOS 0.8µm and installed on experiments Turn to Silicon Germanium 0.35 µm SiGe BiCMOS technology in 2005 Readout for MaPMT and ILC calorimeters Very high level of integration : System on Chip (SoC) Parallel activity of building blocks SkiROCMAROC 2HardROC SPIROC

9. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 9 MAROC : 64 ch MAPMT chip for ATLAS lumi PMTs : 5x5 array of 64 anodes PMT few external components 3*3 cm 2 Chip On Board MAROC1 BOTTOM side

10. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 10 MAROC : 64 ch MAPMT chip for ATLAS lumi –64 channels current preamp –6 bits gain adjustment (G=0-4) per channel –64 discriminator outputs –100% sensitivity to 1/3 photoelectron (50fC). Counting rate up to 2 MHz –Common threshold loaded by internal 10bit DAC (step 3mV) –1 multiplexed charge output with variable shaping 20-200ns and Track & Hold. –Dynamic range : 11 bits (2fC - 5 pC) –Crosstalk < 1% Hold signal Photomultiplier 64 channels Photons Variabl Gain Preamp. Variable Slow Shaper 20-100 ns S&H Bipolar Fast Shaper Unipolar Fast Shaper Gain correction 64*6bits 3 discri thresholds (3*12 bits) Multiplexed Analog charge output LUCID S&H 3 DACs 12 bits 80 MHz encoder 64 Wilkinson 12 bit ADC 64 trigger outputs (to FPGA) Multiplexed Digital charge output 64 inputs

11. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 11 MAROC layout 64 channels –Preamps –Fast shaper 15ns –Discriminators –Slow shaper –Track&Hold –12bit ADC –10bit DAC –Bangap reference –Digital formatting Silicon Germanium –0.35µm BiCMOS –16mm2 area

12. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 12 MAROC performance

13. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 13 ADC performance Wilkinson type 64 channels 12 bits 80 µs conversion time

14. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 14 ILC Challenges for electronics Requirements for electronics –Large dynamic range (15 bits) –Auto-trigger on ½ MIP –On chip zero suppress –Front-end embedded in detector –Ultra-low power : ( « 25µW/ch ) –108 channels –Compactness « Tracker electronics with calorimetric performance » ATLAS LAr FEB 128ch 400*500mm 1 W/ch FLC_PHY3 18ch 10*10mm 5mW/chILC : 100µW/ch W layer Si pads ASIC Ultra-low POWER is the KEY issue

15. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 15 SPIROC overview Silicon Photomultiplier Integrated Read Out Chip –A-HCAL read out –Silicon PM detector –36 channels –Charge measurement (15bits) –Time measurement (< 1ns) –many SKIROC, HARDROC, and MAROC features re-used –Submitted in june 08 Collaboration with DESY –Production in 2008 for Eudet module

16. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 16 SPIROC: One channel schematic

17. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 17 Joël PouthasIPN Orsay “PMm2” (2006 – 2009), funded by the ANR : LAL, IPNO, LAPP and Photonis Replace large PMTs (20”) by groups of smaller ones (12”) – central 16ch ASIC (MAROC like) –12 bit charge + 12 bit time –water-tight, common High Voltage –Only one wire out (DATA + VCC) –Target low cost Reuse many parts from MAROC & SPIROC Application : large water Cerenkov neutrino –1ns time resolution –High granularity –scalability PMm 2 : large photodection area

18. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 18 OMEGA-IHEP/Beijing collaboration Collaboration laid out at Beijing in april 07 around a pekinese duckling Hosting chinese pHD student in OMEGA feb-aug 2008 Common chip for PM readout and sharing building blocks Joint measurements in Beijing and Orsay

19. KEK, 9 may 2007 cdlt FJPPL Neutrino PMM2 R&D 19 TEST BOARD MAROC (COB) 64ch PM socket USB port GPIB port Control Altera