1. VIP1: a 3D Integrated Circuit for Pixel Applications in High Energy Physics Jim Hoff*, Grzegorz Deptuch, Tom Zimmerman, Ray Yarema - Fermilab * jimhoff@fnal.gov

2. Vertical Integration (a.k.a. 3D Integration)– What is it? Several active semiconductor layers “independently” designed Several active semiconductor layers “independently” designed Not necessarily the same function Not necessarily the same function Not necessarily the same technology Not necessarily the same technology Thinned Thinned Bonded together Bonded together Interconnected to one another with deep vias Interconnected to one another with deep vias

3. 8.2 µm 7.8 µm 6.0 µm 3D vias Vertical Integration (a.k.a. 3D Integration)– What is it?

4. Industry’s Interest in Vertical Integration Moore’s Law Reduce R, L, C for higher speed Reduce chip I/O pads Provide increased functionality Reduce interconnect power and crosstalk HEP’s Interest in Vertical Integration Reduced Mass in the Beamline Selectable detector and readout technologies Increased functionality per unit area at a given feature size J. Joly, LETI

5. VIP1: What is it? Features 20 m x 20 m pixel size Binary (hit/no hit) information with analog hit information to improve resolution Double Correlated Sampling Both analog and digital time stamping, each individually capable of resolving 32 time steps per bunch train. Readout between bunch trains Data sparsification with pipelined token passing A single point-to-point serial output line Design for megapixel array, but layout a 64x64 array Low power (assuming power pulsing is used) A Test input per pixel The VIP1 is a 64x64 demonstrator version of a 1k x 1k readout chip for ILC pixel vertex applications. It is designed to conform to ILC standards as they are understood today.

6. VIP1: Overall System Architecture

7. VIP1: Pixel Cell Block Diagram

8. Conversion to a 3D architecture Inter-tier vias are substantial Logical versus physical division of function Layout on one tier impacts layout on other tiers.

9. The Pixel Cell on Tier 1 Tier 3 analog Tier 2 Time Stamp Tier 1 Data sparsification 3D vias D FF X, Y line control Token passing logic Test input circuit OR, SR FF SR-ff for hit storage for the duration of the pulse train. OR to allow universal read Conservative, static, edge- triggered DFF in data sparsification. Dynamic edge- triggered DFF for test input pulses 65 transistors

10. The Pixel Cell on Tier 2 Tier 3 analog Tier 2 Time Stamp Tier 1 Data sparsification 3D vias b0 b1 b2 b3 b4 Analog T. S. 5 bit digital timestamp latched in the pixel from a Gray Code counter on the periphery of Tier 2 Analog time stamp resolution to be determined, but expecting 5 bits Time stamps can be used in alone or in series to create a 10 bit time stamp. 72 transistors

11. The Pixel Cell on Tier 3 Tier 3 analog Tier 2 Time Stamp Tier 1 Data sparsification 3D vias Integrator Discriminator DCS + Readout Schmitt Trigger+NOR CTI Integrator Double correlated sample plus readout Discriminator Chip scale programmable threshold input Capacitive test input (CTI) 38 transistors 2 vias

12. 3D Stacking (of a single pixel) with Vias (step 1) 2000 ohm-cm p-type substrate Buried oxide (BOX), 400 nm thick Tier 1 pixel circuit

13. 3D Stacking (of a single pixel) with Vias (step 2) Bond tier 2 to tier 1 Tier 1 Tier 2

14. 3D Stacking (of a single pixel) with Vias (step 3) Form 3 vias, 1.5 x 7.3 µ m, through Tier 2 to Tier 1

15. 3D Stacking (of a single pixel) with Vias (step 4) Bond tier 3 to tier 2 Tier 3 Tier 2

16. 3D Stacking (of a single pixel) with Vias (step 5) Form 2 vias, 1.5 x 7.3 µ m, through tier 3 to tier 2

17. A 64x64 Array with Perimeter Logic Perimeter circuitry for the ILC Demonstrator chip occupies a small amount of space. Perimeter circuitry for the ILC Demonstrator chip occupies a small amount of space. Area for the perimeter logic could be reduced in future designs. Area for the perimeter logic could be reduced in future designs. 64 x 64 array with perimeter logic Blow up of corner of array

18. Status The design was submitted in October of last year. It was due in August of this year. The design was submitted in October of last year. It was due in August of this year. We expect delivery any day and hope to present experimental results in the conference record or in a TNS paper. We expect delivery any day and hope to present experimental results in the conference record or in a TNS paper. This design was fabricated as part of a multi-project wafer run supported as a DARPA R&D effort. This was the second such run. This design was fabricated as part of a multi-project wafer run supported as a DARPA R&D effort. This was the second such run. A third MPW run is planned for next year. A third MPW run is planned for next year.

19. Background Slides

20. Output Assume 1000 x 1000 array (1000 pixels/row) Token skip frequency = 0.2ns Time to scan 1 row =.200 ns x 1000 = 200 ns (simulated) Time to readout cell = 30 bits x 20 ns/bit = 600 ns Max hits/chip = 250 hits/mm 2 x 225 mm 2 = 56250 hits/chip. For 50 MHz readout clock and 30 bits/hit, readout time = 57250 hits x 30 bits/hit x 20 ns/bit = 34 msec