1. Page 1EL/CCUT T.-C. Huang May 2004 TCH CCUT Introduction to IC Test Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech. Email: tch@dragon.ccut.edu.tw 2004/05/10

2. Page 2EL/CCUT T.-C. Huang May 2004 TCH CCUT Syllabus & Chapter Precedence Introduction Modeling Logic SimulationFault Modeling Fault Simulation Testing for Single Stuck Faults Test Compression Built-In Self-Test Design for Testability

3. Page 3EL/CCUT T.-C. Huang May 2004 TCH CCUT Aliasing Test Generator Good Circuit Bad Circuit Correct Response Unobservable Aliasing Testable Test Generator Good Circuit Bad Circuit Correct Response Error Response Compress Test Generator Good Circuit Bad Circuit Correct Response Error Response Non-alias Compress Test Generator Good Circuit Bad Circuit Correct Response Error Response

4. Page 4EL/CCUT T.-C. Huang May 2004 TCH CCUT Compression Rate Original Digital Signal with N Bytes Compressed file with N c Bytes Uncompressed file with M Bytes with distortion Original Test Vectors for Fault Set, F, with N patterns Compressed Vectors for Fault Set, G, with N c patterns Test (Vector) Compression Original Test Results for Fault Set, F, with N patterns Compressed Results for Fault Set, G, with N c patterns Test Signature Compression Aliased iff F≠G, alias rate =

5. Page 5EL/CCUT T.-C. Huang May 2004 TCH CCUT Test Compression Techniques 1.One-Counting #1’s in response sequence 2.Transition Counting Transition btw responses r t and r t+1 3.Parity Checking 0-parity or 1-parity 4.Syndrome Checking  1-Counting; 1-ratio in the K-map 5.Signature Analysis Based on CRC (Cyclic Redundancy Check) using LFSR (Linear Feedback Shift Register)

6. Page 6EL/CCUT T.-C. Huang May 2004 TCH CCUT One-Counting Circuit under Test (CUT) 101101101101 10011001 110001110001 10101010 001100001100 01110111 111111111111 11101110 000100000100 10001000 Transition-Counting 1C=11 Parity Check → Odd Compression Rate: Aliasing Rate:

7. Page 7EL/CCUT T.-C. Huang May 2004 TCH CCUT Syndrome Test The Syndrome S is the normalized number of ones in the result bit stream based on exhausting test. That is, the one-count in the deterministic K-map. The syndrome probability can be calculated. AND OR NAND NOR XOR S1S2S1S2 S 1 +S 2 -S 1 S 2 1-S 1 S 2 1-S 1 -S 2 +S 1 S 2 S 1 +S 2 -2S 1 S 2 S1S1 S2S2 S Not practical in circuitry with many inputs.

8. Page 8EL/CCUT T.-C. Huang May 2004 TCH CCUT Linear Logic Circuit A linear (logic) circuit preserved the principle of superposition and is constructed from: Delay Flipflops Modulo-2 Adder Modulo-2 Scalar Multiplier D xy = Dx x c cxx cx c x y x+y x y

9. Page 9EL/CCUT T.-C. Huang May 2004 TCH CCUT Linear Feedback Shift Register, LFSR An LFSR can be mapped into a feedback linear circuit with DFFs & XORs in a modulo-2 domain. Canonical Forms: Type I (Direct Form, External Form): Type II (Indirect Form, Internal Form): D1D1 C1C1 + D2D2 C2C2 + D3D3 C3C3 + D4D4 C4C4 + D n-1 C n-1 + DnDn C n =1 D1D1 D2D2 D3D3 D4D4 D n-1 DnDn C n =1 C n-1 + C n-2 + C n-3 + C n-4 + C1C1 +

10. Page 10EL/CCUT T.-C. Huang May 2004 TCH CCUT Example D1D1 D2D2 + D3D3 So=So=001 S1=S1=100 S2=S2=010 S3=S3=101 S4=S4=110 S5=S5=111 S6=S6=011 S7=S7=001 So=So=100 100101110 Generating Function

11. Page 11EL/CCUT T.-C. Huang May 2004 TCH CCUT Why LFSR ? Simple and Regular Structure Compatible with scan DFT design Capable of exhaustive and/or pseudo exhaustive testing Low aliasing probability.

12. Page 12EL/CCUT T.-C. Huang May 2004 TCH CCUT Characteristic polynomial P(x) Characteristic Polynomials of an LFSR D1D1 C1C1 + D2D2 C2C2 + D3D3 C3C3 + D4D4 C4C4 + D n-1 C n-1 + DnDn C n =1 Generating function Initial State = If IS=1 at D n.

13. Page 13EL/CCUT T.-C. Huang May 2004 TCH CCUT Maximum Length Sequence Let p be the generating period, P(x) divides into 1-x p. Reciprocal polynomial of P(x) is P*(x)=x n P(1/x). If G(x) of an n-stage LFSR has period 2 n-1, then it is called a maximum-length sequence (MLS) and the characteristic polynomial is called a primitive polynomial. An irreducible polynomial P(x) is with odd number of terms and it’s primitive if min(k)=n for. Primitive (MLS) Polynomials Irreducible polynomials

14. Page 14EL/CCUT T.-C. Huang May 2004 TCH CCUT An Algorithm to Search ML-LFSR 1.For i=1, x+1 is a primitive polynomial; 2.Put searched irreducible polynomials into a queue. 3.Check a polynomial of order n with the irreducible polynomial of order less than square-root of n. 4.If it is irreducible, check if k is the smallest integer such that it divides into 1+x k, where k=2 n-1.

15. Page 15EL/CCUT T.-C. Huang May 2004 TCH CCUT Examples of Primitive Polynomials D1D1 D2D2 + D3D3 D1D1 D2D2 D3D3 + D1D1 D2D2 + D3D3 D1D1 D2D2 D3D3 + primitive Note that P*(x) must not be primitive even if P(x) primitive.

16. Page 16EL/CCUT T.-C. Huang May 2004 TCH CCUT Characteristics of MLS 1.The number of ones in an L-Sequence differs from the number of zeros by 1. 2.An L-Sequence produces an equal number of runs of 1s and 0s. 3.In every L-Sequence, one half the runs have length 1, one fourth have length 2, one eighth have length 3, and so forth. 4.The above properties of randomness make feasible the use of LFSRs as test sequence generators in BIST (Built-In Self-Test, introduced in next chapter) circuitry. 5.LFSRs used as counters are taken advantage of its speed (usually with only the exclusive gate for propagation time of the combinational circuits)

17. Page 17EL/CCUT T.-C. Huang May 2004 TCH CCUT Pseudo Randomness Example: G%(2 n -1)=G%63 G%2 (n-1) =G%8G%2 (n-1) =G%9 G%2 (n-1) =G%7

18. Page 18EL/CCUT T.-C. Huang May 2004 TCH CCUT LFSR with the All-Zero Pattern D1D1 C1C1 + D2D2 C2C2 + D3D3 C3C3 + D4D4 C4C4 + D n-1 C n-1 + DnDn C n =1 Reset all FFs

19. Page 19EL/CCUT T.-C. Huang May 2004 TCH CCUT (Pseudo) Random Pattern Generator (RPG) RPG Typically, 32~128 bits Scan chain Typically, length of 500~3000 CUT SA Typically, 32~128 bits

20. Page 20EL/CCUT T.-C. Huang May 2004 TCH CCUT Signature Analyzer (SA) D1D1 C1C1 + D2D2 C2C2 + D3D3 C3C3 + D4D4 C4C4 + D n-1 C n-1 + DnDn C n =1 or Generating function Initial State = Input Stream of length L Quotient Remainder Characteristic polynomial P(x) Signature Analysis is a compression technique based on the concept of cyclic redundancy checking (CRC). We use S(x) to denote the input stream (instead of G(x) that is confused in textbook).

21. Page 21EL/CCUT T.-C. Huang May 2004 TCH CCUT Signature Analyzer (SA) RPG as a special case of SA: S(x)=0 and There are 2 L possible input stream, 2 L-n streams produce a signature. Aliasing rate (proportion of masking error streams is SA with >1 non-0 coefficients detects all single-bit errors (e.g. x+1 ).

22. Page 22EL/CCUT T.-C. Huang May 2004 TCH CCUT Two Different Application Examples SA1SA2 EncryptionDecryption Communication X(t)X(t-d) ???? PRPGSA Testing CUT

23. Page 23EL/CCUT T.-C. Huang May 2004 TCH CCUT Multiple Input Signature Register (MISR) Only Type II (Internal) forms can be improved to be multiple-input. D1D1 D2D2 D3D3 D4D4 D n-1 DnDn C n =1 C n-1 + C n-2 + C n-3 + C n-4 + C1C1 + CUT Can be RPG or Non-Random Patterns (e.g., Counter)

24. Page 24EL/CCUT T.-C. Huang May 2004 TCH CCUT Multiple Inputs Used in Seed Loading D1D1 D2D2 D3D3 D4D4 D n-1 DnDn C n =1 C n-1 + C n-2 + C n-3 + C n-4 + C1C1 + Seed base ROM or Register

25. Page 25EL/CCUT T.-C. Huang May 2004 TCH CCUT Integrated RPG/MISR into Scan Cells Combinational Circuit Di Si Dn Ci Normal MISR RPG Scan

26. Page 26EL/CCUT T.-C. Huang May 2004 TCH CCUT Syllabus & Chapter Precedence Introduction Modeling Logic SimulationFault Modeling Fault Simulation Testing for Single Stuck Faults Test Compression Built-In Self-Test Design for Testability ( I )

27. Page 27EL/CCUT T.-C. Huang May 2004 TCH CCUT Built-In Self-Test (BIST) 1.To Reduce input/output pin signal traffic. 2.Permit easy circuit initialization and observation. 3.Eliminate as much test pattern generation as possible. 4.Achieve fair fault coverage on general class of failure mode. 5.Reduce test time. 6.Execute at-speed testing. 7.Test circuit during burn-in.

28. Page 28EL/CCUT T.-C. Huang May 2004 TCH CCUT Issues 1.Area overhead 2.Performance degradation 3.Fault coverage 4.Ease of Implementation 5.Capability for system test 6.Diagnosis capability

29. Page 29EL/CCUT T.-C. Huang May 2004 TCH CCUT Typical BIST Techniques 1.Stored Vector Based 1.Microinstruction support 2.Stored in ROM 2.Algorithmic Hardware Test Pattern Generators 1.Counter 2.Linear Feedback Shift Register 3.Cellular Automata Design with BIST TestGood (or Not)