1. Computer Organization Department of CSE, SSE Mukka Chapter 6 : ARITHMETIC www.bookspar.com | Website for students | VTU NOTES

2. Addition and Subtraction of signed numbers  Sum s i can be implemented with XOR gate.  Carry-out function c i+1 can be implemented with a two- level AND-OR logic circuit.  A cascaded connection of n full adder blocks can be used to add two n-bit numbers – called as n-bit ripple carry adder  The carry-in C0 into least significant-bit position provides a convenient means of adding 1 to a number  For example forming 2’s complement of a number involves adding 1 to 1’s complement of the number www.bookspar.com | Website for students | VTU NOTES

3. s i = c i +1 = Figure 6.1. Logic specification for a stage of binary addition. 13 7 +Y 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Example: 1 0 ==0 0 1 1 1 1 1 0 0 1 1110 Legend for stagei x i y i Carry-inc i Sums i Carry-outc i+1 X Z + 6 0 + x i y i s i Carry-out c i+1 Carry-in c i x i y i c i x i y i c i x i y i c i x i y i c i x i y i c i  = +++ y i c i x i c i x i y i ++ www.bookspar.com | Website for students | VTU NOTES

4. Full adder (FA) c i y i x i c i1+ s i (a) Logic for a single stage FA c 0 y 1 x 1 s 1 FA c 1 y 0 x 0 s 0 FA c n1- y n1- x n1- c n s n1- (b) Ann-bit ripple-carry adder n-bit c 0 y n x n s n c n y 0 x n1- s 0 c kn s k1-  n x 0 y n1- y 2n1- x 2n1- y kn1- s n1- s 2n1- s kn1- (c) Cascade of k n-bit adders x kn1- Figure 6.2. Logic for addition of binary vectors. Most significant bit (MSB) position Least significant bit (LSB) position c i y i x i c i y i x i x i c i y i s i c i1+ adder n-bit adder n-bit adder www.bookspar.com | Website for students | VTU NOTES

6. Figure 6.4. 4-bit carry-lookahead adder. Carry-lookahead logic B cell (b) 4-bit adder (a) Bit-stage cell s 3 P 3 G 3 c 3 P 2 G 2 c 2 s 2 G 1 c 1 P 1 s 1 G 0 c 0 P 0 s 0. c 4 x 1 y 1 x 3 y 3 x 2 y 2 x 0 y 0 G i c i... P i s i x i y i G 0 I P 0 I B cell www.bookspar.com | Website for students | VTU NOTES