1. מבנה מחשב תרגול 2

2. 2 Boolean AND Operation 10 000 101 Truth Table Equivalent Gate Different notations:

3. 3 Boolean OR Operation 10 100 111 Truth Table Equivalent Gate Different notations:

4. 4 Boolean NOT Operation 10 01 Truth Table Equivalent Gate Different notations:

5. 5 Boolean NAND Operation 10 110 011 Truth Table Equivalent Gate

6. 6 Boolean NOR Operation 10 010 001 Truth Table Equivalent Gate

7. 7 Boolean XOR Operation 10 100 011 Truth Table Equivalent Gate Different notations:

8. 8 How to implement XOR? Which is Better?

9. Example What does the following combinational circuit decide ? 9

10. 10 Boolean Equalities (1) Rules of Associativity, Commutation. Other rules:

11. 11 Boolean Equalities (2) Distribution deMorgan

12. 12 Example (1): Simplify the expression Compare number of gates

13. 13 Example (2): Simplify the expression

14. 14 Evaluating an Expression (1) Let’s look at the first expression:  1 1 1 1 1

15. 15 Evaluating an Expression (2) Let’s look at the first expression:  1 1 =1 1 1

16. 16 Truth Table 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 1 2 3 4 5 6 7 We get Different Notation for

17. 17 Disjunctive Normal Form 0 0 0 0 0 0 0 0 1 1 11 1 1 1 1 1 1 1 1 0 1 4 5 7 It’s easy to transform a DNF formula to its equivalent gates’ representation

18. 18 Disjunctive Normal Form

19. 19 New Components l Two major components of combinational logic are – multiplexors & decoders. l 2-input multiplexor (or selector) is implemented with gates below abab s c symbol abab c s gate implementation

20. Multiplexors (MUXes) A device that selects one of several input signals and forwards it into a single line. Also called a data selector 20

21. 21 Multiplexors (MUXes) Multiplexors can have any number of inputs (in theory) Multiplexors can apply to buses  multiplied for many lines. – Example: 1 x 2 multiplexor on 32 bits bus. 0123456701234567 s0 c 3 X 8 multiplexor s1 s2 a31 b31 s c31 a30 b30 c30............ a0 b0 c0 M M M abab s c 32 symbol

22. Encoders An encoder conv- erts information from one format to another. For the purposes of speed, secrecy, security, or saving space by shrinking size. 22 2 n input lines, and at most only one of them will ever be high, produces n-bit output lines. ( Other options – don’t cares )

23. Decoders Reverse operation of an Encoder undoing the encoding so that the original information can be retrieved Combinational circuit that converts binary information from n input lines to a maximum of 2 n unique output lines. The same method used to encode is usually just reversed in order to decode. Results in sending less information !!! 23

24. 24 Decoders Each combination of the inputs enables exactly one output 0123456701234567 DECODER 012012 3 X 8 Decoder OutputsInputs O0O1O2O3O4O5O6O7I0I1I2 10000000000 01000000100 00100000010 00010000110 00001000001 00000100101 00000010011 00000001111

25. Adders A digital circuit that performs addition of numbers. The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The carry signal represents an overflow into the next digit of a multi-digit addition. 25

26. Full Adder from Half Adders Half adder Full adder from 2 half adders + or gate abab Cout sum Cin abab Cout sum We will look into adders more closely when we examine the ALU

27. 27 Flip-Flops What happens if we create a circle in the logic gates diagram? a Circuit that has two stable states and can be used to store state information. Can be made to change state by signals applied to one or more control inputs. This is a S-R Flip-Flop

28. An S-R flip-flop: S – set. R Reset. Initial state Q=1 and R = 0 S = 1 : Changes Q to 1. R = 1 S = 0 : Changes Q to 0. R=1 S=0 Q=0 Q=1 R=0 S=1 Q=1 Q=0 R=0 S=0 Q=0 Q=1 R=0 S=0 Q=1 Q=0 R = 1 S = 1 : illegal

29. S-R Latch (Or S-R Flip-Flop)  Feedback is the key to memory/state elements.  Once a value is fed to the element, it circulates inside the element and renews itself, even after the input is turned off.  Other memory devices can be built from the basic latch. R SR S Q Q QQRS Save 00 1010 0101 0011 Illegal

30. Clocked "D" Latch This latch has one input, called "D". When the clock is low, AND gates force zero on all inputs to the S-R latch  no change in state. When clock is high, the value at D sets the "S" input of the latch; inverted D sets the "R" input of the latch. Cloc k D Q Q S-R Flip-Flop With a Clock

31. 31 D-Flip-Flop (1) On each clock pulse the FF should be meaningful Therefore the R and S lines should be opposite If so do we still need both of them?

32. 32 D Flip-Flop (2) D Flip-Flop when the clock is pulsing: 100 011

33. "D" Latch Clocking Waveforms The output "D" responds to the change in input, a characteristic delay after the clock goes high. Cloc k D Q Q DCQDCQ t delay t t

34. 34 Edge Triggered "D" flip-flop The first latch is called the master, the second latch is called the slave l When the clock goes high, the first D latch (master) accepts the change in input l Because of the inverter, the change is blocked from moving on the second D latch (slave). l When the clock goes low, the slave latch accepts the change in input D Clock Q Q D Latch D C Q D Latch D C Q

35. 35 Registers Registers can be built from a series of ET D latches connected to the same clock Clock ET-D Latch D C Q ET-D Latch D C Q ET-D Latch D C Q... ET-D Latch D C Q D0D1D2D(n-1) Q0Q1Q2Q(n-1)

36. The Register File Modern digital systems are based on logic with state variables, which are changed according to a clock.  The system consists of two types of logic -- combinational and sequential. – Combinational logic  a change in inputs directly causes a change in output, after a characteristic delay. Different from sequential logic which only changes on the clock. – Sequential logic contains state elements or memory elements. State elemen t 1 State elemen t 2 Combination al Logic The simplest type of clocking system to understand is built with edge triggered state elements. The diagram shows a system which clocks on the leading edge of the clock. leading edge leading edge clock period

37. 37 Register File Implementation of double read port register 0 register 1... register 6 register 7 MUXMUX MUXMUX data 1 data 2 read reg 1 read reg 2 3 bits 32 bits read reg 1 read reg 2 write reg write data write enable read data 1 read data 2 3 bits 32 bits 1 bit

38. 38 Write Port Implementation n-to-1 decoder 01..6701..67 register 0 register 1...... register 6 register 7 CDCD CDCD CDCD CDCD CDCD...... write enable write data Reg # 32 bits 1 bit 3 bits Clock 1 bit