1. Elements of discrete devices synthesis (module T170M012) 2012 Kaunas university of technology Electronic and measurement systems dep. Doc. dr. Žilvinas Nakutis

2. total 392 Goal of the synthesis  Translate higher abstraction level presentation (for example algoritmic) to the lower abstraction level presentation (for example logic gates)  Logic synthesis – RTL description (VHDL, Verilog) transformation to logic gates

3. total 393 Variety of logic device descriptions

4. total 394 Digital logic synthesis Digital logic synthesis is designing of logic gate circuit according to the given logic expression or truth table. Task: Draw the circuit of the devices, described by the truth table (Digital design with CPLD applications and VHDL, 2000 psl. 68).

5. total 395 Sum-of-Products and Product-of-Sums forms   Product term is the member in logic equation representing logic multiplication of two or several signals, for example A & B.   Minterm is the member representing logic multiplication of all input signals or inverted input signals   Sum term is the member representing logic sum of two or several signals, for example A | B | D   Maxterm is the member representing logic sum of all input signals or inverted input signals  SOP  Sum-of-products (SOP) (A & B & C)+(!A & !B & C)+(A & B & !C)  POS  Product-of-sums (POS) (A+B+C) & (A+!B+!C) & (A+B+!C)

6. total 396 Sum of products (SOP) form Minterms Y=1

7. total 397 Schematics from Sum of products form Y ABC

8. total 398 Task: synthesis of XOR and NXOR gates

9. total 399 Product of sums (POS) form Minterms !Y=1 Invert both sides and apply De Morgano rule Task: Propose how to derive the POS form directly from truth table

10. total 3910 Sumary of SOP and POS forms Need to do reduction

11. total 3911 Features of boolean algebra  Comutativity: A & B = B & A, A + B = B + A  Associativity: (A & B) & C = A & (B & C), (A + B) + C = A + (B + C),  Distributivity: A & (B + C) = A & B + A & C. Task: Check the associativity of the XOR (^) logic function. Using features of boolean algebra SOP and POS form can be reduced in order to minimize number of needed gates.

12. total 3912 Theorems of Boolean algebra  De Morgan theorems  Other rules

13. total 3913 Boolean (bit) algeba theorems

14. total 3914 Forms reduction using Karnaugh maps   Karnaugh maps (K-maps) methods is used to generate optimized (simplified) logic expression from the truth table.   Karnaugh (French mathematitan Maurice Karnaugh) diagram (angl. Karnaugh map or K-map,KV-map (other inventor Edward W. Veitch)– is another form of truth table, where each combination of logic inputs (minterm) is represented by the corresponding cell.   Edward W. Veitch used the method in 1952, Maurice Karnaugh – in 1953.   Karno diagramos sudaromos taip, kad gretimuose jos kvadratėliuose skirtųsi tik vieno loginio kintamojo reikšmė, o visų kitų sutaptų. Predko, Myke. Digital Electronics Demystified, McGraw-Hill, 2004 (Ebrary bibliotekoje) http://www.facstaff.bucknell.edu/mastascu/eLessonsHTML/Logic/Logic3.html

15. total 3915 Key terms   Karnaugh map A graphical tool for finding the maximum SOP or POS simplification of a Boolean expression. A Karnaugh map works by arranging the terms of an expression in such a way that variables can be canceled by grouping minterms or maxterms.   Cell The smallest unit of a Karnaugh map, corresponding to one line of a truth table. The input variables are the cell’s coordinates, and the output variable is the cell’s contents.   Adjacent cell Two cells are adjacent if there is only one variable that is different between the coordinates of the two cells. For example, the cells for minterms ABC and ABC are adjacent.   Pair A group of two adjacent cells in a Karnaugh map. A pair cancels one variable in a K-map simplification.   Quad A group of four adjacent cells in a Karnaugh map. A quad cancels two variables in a K-map simplification.   Octet A group of eight adjacent cells in a Karnaugh map. An octet cancels three variables in a K-map simplification.

16. total 3916 K-maps example Initial function

17. total 3917 Rules for finding circles (contours) 1. One circle can include only the number multiple to 2 n adjacent cells (for example 3 cells can not compose a circle). This way we can circle 1, 2, 4, 8, etc. adjacent cells. Note: Adjacent cells are also those that are at the opposite sides of the map.

18. total 3918 Rules for finding circles (2) 2. Circles may intersect, i.e. one cell can be included in to two or more circles. If there exists the circle containing only cells that are already included in to other circles then this circle is redundant and not needed for the following steps.

19. total 3919 Rules for finding circles (3) 3. Start circling groups larger than 2. In the example bellow groups from 4=2 2 are circled.

20. total 3920 Rule for writing the optimized logic expression from K-map  Logic expression is derived in the SOP from. Each product term corresponds to one circle in the K-map.  The product term corresponding the circle is composed from input signals whose value are constant (0 or 1) in all the cells of the circle.  If the signal value is equal to 0 than inverted signal substituted in the expression; when the signal value is 1, then signal enters expression directly.

21. total 3921 Write the optimized logic expression from K-map (example) Y=(!B*C)+(B*!С) +(A*С)Y=A+C Y=(!B*C)+(B*!С) +(A*!С)

22. total 3922 K-map application example

23. total 3923 Task No.1 (synthesis using K-maps) BC BCA00011110 01011 10111 Y = (!A*!C) + (A*С) + B

24. total 3924 Task No.2 (synthesis using K- maps) CD CD AB 00011110 000000001 01111 11111 1010101011 Y = (A*!B*D) + (B*!D) + C*D

25. total 3925 K-maps application with don’t care outputs (denoted by X) BC BCA00011110 00010 1111X Y = (A*!B) + (B*С) Y = (B*С) + A Only cells with 1’s are circled Cells with 1’s and X’s are circled Note: Both equations are correct, but the second needs less gates for implementation

26. total 3926 Disadvantages of K-maps  Suitable for manual optimization but hard to implement as computer program  Working manually with large K-maps typing errors can occur often  Suitable up to 6 input signals, practically usable up to 4 input signals

27. total 3927 Other algorithms for logic functions minimization  Quine–McCluskey algorithm (http://en.wikipedia.org/wiki/Quine- McCluskey_algorithm): http://en.wikipedia.org/wiki/Quine- McCluskey_algorithmhttp://en.wikipedia.org/wiki/Quine- McCluskey_algorithm Can be described mathematically in the way suitable fro implementation in computer program Can be described mathematically in the way suitable fro implementation in computer program Suitable for small number of inputs/outputs because computational requirements grow exponentially with the number of inputs/outputs Suitable for small number of inputs/outputs because computational requirements grow exponentially with the number of inputs/outputs  Espresso heuristic logic minimizer - de-facto standard

28. total 3928 Espresso heuristic logic minimizer  Introduced in 1980 in Brayton’s Berkeley university  It is a computer program, that utilizes heuristic minimization algorithms  The optimal minimization result is not guarateed  Computational requirements are much less compared to other algorithms  Practicaly no constraints on the number of inputs/outputs. The task was solved with several tens of inputs/outputs.  The circuit is mapped to (synthesized from) the selected basic gates. Therefore, the method is well suited for CPLD and FPGA synthesis  The algorithm has many modifications  Implemented in many synthesis programs

29. total 3929 Logic Friday – free program for logic synthesis based on Espresso algorithm Example: Truth table of decoder of 7-segment indicator

30. total 3930 Selection of basic gates  Wanted implementation using 2NAND and NOT gates

31. total 3931 Synthesis result (total 30 gates)

32. total 3932 Selection of other basic gates  Wanted implementation using 2NOR and NOT gates

33. total 3933 Synthesis result (total 36 gates)

34. total 3934 Multi-level synthesis  At the beginning synthesis tools design a multilevel network from the Register-Transfer- Level (RTL) description  The network is then optimized with the technology independent approach  Finally, optimized logic expressions are mapped to the circuit of logic gates. The mapping process encounters constraints concerning available gates (AND, OR, etc.) and requirements of delays, power consumption, die area, etc.

35. total 3935 Synthesis for FPGA  Using multiplexors  Using Look Up Tables (LUT)

36. total 3936 Logic synthesis, using multiplexors (MUX) http://dropzone.tamu.edu/~wshi/475/MIT_Logic_Synthesis.pdf

37. total 3937 Implementation of combinational logic using MUX

38. total 3938 Multiplexors are universal devices

39. total 3939 General structure of MUX

40. total 3940 Distributed decoding logic