1. VAX-11/780 A VIRTUAL ADDRESS EXTENSION TO THE DEC PDP-11 FAMILY VAX-11/780 A VIRTUAL ADDRESS EXTENSION TO THE DEC PDP-11 FAMILY W.D.STRECKER W.D.STRECKER

2. Motivation -Limited virtual address space -Limited virtual address spaceFeatures - extension of virtual address from 16 bits to 32 bits. - extension of virtual address from 16 bits to 32 bits. -with 8 bit byte the basic addressable unit, the extension -with 8 bit byte the basic addressable unit, the extension provides a virtual address space of 4.3GB. provides a virtual address space of 4.3GB. One of the main goals of VAX-11 was maximum PDP-11 compatibility. One of the main goals of VAX-11 was maximum PDP-11 compatibility. -VAX-11 includes two modes -VAX-11 includes two modes -compatibility mode. -compatibility mode. -provides basic PDP-11 instruction set less only privileged -provides basic PDP-11 instruction set less only privileged instructions and floating point instructions. instructions and floating point instructions.

3. -native mode - native mode data types and formats are identical to PDP-11. - native mode data types and formats are identical to PDP-11. As a consequence VAX-11 native mode assembly language programming As a consequence VAX-11 native mode assembly language programming is similar to PDP-11. is similar to PDP-11. -VAX-11/780 uses the same peripheral buses (Unibus and Massbus) -VAX-11/780 uses the same peripheral buses (Unibus and Massbus) and the same peripherals. and the same peripherals. -The VAX/VMS file system is same as used in RSX-11M/IAS -The VAX/VMS file system is same as used in RSX-11M/IAS operating systems permitting interchange of files and volumes. operating systems permitting interchange of files and volumes. -VAX-11 high level language compilers accept the same source languages -VAX-11 high level language compilers accept the same source languages as equivalent PDP-11 compilers and the execution of compiled programs as equivalent PDP-11 compilers and the execution of compiled programs gives the same result. gives the same result.

4. VAX-11 NATIVE ARCHITECTURE Processor state - VAX-11 is organized around a general register processor state. This - VAX-11 is organized around a general register processor state. This organization was favored because access to operands stored in general organization was favored because access to operands stored in general registers is fast and because only small number of bits in an instruction registers is fast and because only small number of bits in an instruction are used to designate a register. are used to designate a register. -Registers are used with large set of addressing modes which permit flexible -Registers are used with large set of addressing modes which permit flexible operand addressing methods. operand addressing methods. -VAX-11 has 16 32 bit general registers which are used for both -VAX-11 has 16 32 bit general registers which are used for both fixed and floating point operands. (PDP-11 has 8 16 bit general registers fixed and floating point operands. (PDP-11 has 8 16 bit general registers and 6 64 bit floating point registers). Merged set of fixed and floating point and 6 64 bit floating point registers). Merged set of fixed and floating point registers were favored as it simplified programming. registers were favored as it simplified programming.

5. Four registers in VAX-11 architecture are assigned special meaning. Four registers in VAX-11 architecture are assigned special meaning. They are They are Program counter (R15) – contains address of next byte to be Program counter (R15) – contains address of next byte to be interpreted in instruction stream. interpreted in instruction stream. Stack pointer(R14) – contains the address of the top of the processor Stack pointer(R14) – contains the address of the top of the processor defined stack used for procedure and interrupt linkage. defined stack used for procedure and interrupt linkage. Frame pointer(R13) – The VAX-11 procedure calling convention builds Frame pointer(R13) – The VAX-11 procedure calling convention builds a data structure on stack called stack frame. FP contains the a data structure on stack called stack frame. FP contains the address of this structure. address of this structure. Argument pointer(R12) – The VAX – 11 procedure calling convention Argument pointer(R12) – The VAX – 11 procedure calling convention uses a data structure called argument list. AP contains the address uses a data structure called argument list. AP contains the address of this structure. of this structure.

6. DATA TYPES AND FORMATS -Integer data type -Integer data type -8 bit byte, 16 bit word,32 longword, 32 bit quadword. -8 bit byte, 16 bit word,32 longword, 32 bit quadword. -Floating data type -Floating data type -32 bit floating(7), 64 bit floating(16). -32 bit floating(7), 64 bit floating(16).

7. -Variable bit field data type -Variable bit field data type - 0 to 32 bits located arbitrarily with respect to addressable byte - 0 to 32 bits located arbitrarily with respect to addressable byte boundaries. boundaries. - Character string data type - Character string data type -0 to 65535 contiguous bytes. Specified by two operands i.e the -0 to 65535 contiguous bytes. Specified by two operands i.e the length and starting address of the string. length and starting address of the string. -Decimal string data type - 0 to 31 digits. Specified by two operands i.e length and starting - 0 to 31 digits. Specified by two operands i.e length and starting address. address. -the Primary data type is packed decimal which contains two digits in -the Primary data type is packed decimal which contains two digits in each byte and byte containing least significant digit has single digit. each byte and byte containing least significant digit has single digit.

8. An instruction consists of one or two byte opcode An instruction consists of one or two byte opcode followed by specifications of operands. An operand followed by specifications of operands. An operand specification is one to 10 bytes in length and consists of one or two specification is one to 10 bytes in length and consists of one or two byte operand specifier followed by specifier extension. byte operand specifier followed by specifier extension. Address modes : Register mode Register mode -designated register contains the operand. -designated register contains the operand. Register deferred mode Register deferred mode -designated register contains the address of the operand. -designated register contains the address of the operand. Autoincrement mode Autoincrement mode -contents of the designated register is used as the -contents of the designated register is used as the address of the operand and is incremented by the size of address of the operand and is incremented by the size of the operand. (PC - immediate mode) the operand. (PC - immediate mode)

9. Autoincrement deferred mode Autoincrement deferred mode -contents of the designated register are used as the address of -contents of the designated register are used as the address of longword in memory which contains the address of the operand. longword in memory which contains the address of the operand. (PC-absolute mode) (PC-absolute mode) Displacement mode Displacement mode -displacement is added to the contents of the designated register -displacement is added to the contents of the designated register to form the operand address. (PC- relative mode) to form the operand address. (PC- relative mode) Displacement deferred mode Displacement deferred mode -displacement is added to the designated register to form the address -displacement is added to the designated register to form the address of longword containing the operand address. (PC – relative deferred of longword containing the operand address. (PC – relative deferred mode) mode)

10. Literal mode Literal mode -operand specifier itself contains a 6-bit literal which is the operand. -operand specifier itself contains a 6-bit literal which is the operand. Index mode Index mode - not really a mode but a prefix operator for any other mode which - not really a mode but a prefix operator for any other mode which evaluates the address. evaluates the address. - the index mode prefix is cascaded with the operand specifier for that - the index mode prefix is cascaded with the operand specifier for that mode to form an aggregate two byte operand specifier. mode to form an aggregate two byte operand specifier. -the base operand specifier is used to evaluate a base address. A -the base operand specifier is used to evaluate a base address. A copy of the contents of the register designated in the index prefix copy of the contents of the register designated in the index prefix is multiplied by the size of the operand and added to the base address is multiplied by the size of the operand and added to the base address to give the final operand address. to give the final operand address.

11. 176 176 10 5 10 5 56 56 12 6 12 6 270 270 MOVW opcode Byte register mode(R5) Displacement Word displacement mode(R6) Displacement MOVW 56(R5), 270(R7)

12. Instruction set Instruction set Integer logic and arithmetic Integer logic and arithmetic - along with conventional arithmetic and logical instructions a number o of optimizations are included like clear, test, - along with conventional arithmetic and logical instructions a number o of optimizations are included like clear, test, increment, decrement. Extended multiply and divide and add increment, decrement. Extended multiply and divide and add with carry and subtract with carry were provided to support long- with carry and subtract with carry were provided to support long- word precision integer operations. word precision integer operations. Floating point instructions Floating point instructions -along with conventional several specialized floating point instructions -along with conventional several specialized floating point instructions were included like extended modulus instruction which multiplies two were included like extended modulus instruction which multiplies two floating point operands and stores the integer and fraction parts of floating point operands and stores the integer and fraction parts of the product in separate result operands. the product in separate result operands.

13. Address instructions Address instructions -move address instruction stores in the result operand the effective -move address instruction stores in the result operand the effective address of the source operand. address of the source operand. -push address optimizations push on the stack the effective address of -push address optimizations push on the stack the effective address of the source operand. the source operand. Field instruction Field instruction - the extract field instruction extracts 0-32 bit field, sign or zero extended - the extract field instruction extracts 0-32 bit field, sign or zero extended if it is less than 32 bits, and store the result in longword operand. if it is less than 32 bits, and store the result in longword operand. -compare field instructions compare a field against a longword operand. -compare field instructions compare a field against a longword operand.

14. Control instructions Control instructions -There is a complete set of conditional branches supporting both signed -There is a complete set of conditional branches supporting both signed and unsigned interpretation of various data types. These branches and unsigned interpretation of various data types. These branches test the condition codes and take one byte PC relative branch test the condition codes and take one byte PC relative branch displacement. displacement. -There are three conditional branch instructions -There are three conditional branch instructions -first taking one byte PC relative displacement. -first taking one byte PC relative displacement. -second taking a word PC relative displacement. -second taking a word PC relative displacement. -third called jump taking a general operand specification. -third called jump taking a general operand specification. -There are a set of branch instructions which branch on the state of single bit and, depending on the instruction set, clear or leave unchanged -There are a set of branch instructions which branch on the state of single bit and, depending on the instruction set, clear or leave unchanged that bit. that bit.

15. Queue instructions Queue instructions -represented by doubly linked circular list. -represented by doubly linked circular list. -instructions are provided to insert an item into a queue or to remove -instructions are provided to insert an item into a queue or to remove an item from the queue. an item from the queue. Character string instructions Character string instructions -general move character instruction takes five operands specifying -general move character instruction takes five operands specifying lengths and starting address of the source and destination strings. lengths and starting address of the source and destination strings. -an optimized move character instruction assumes the string length are -an optimized move character instruction assumes the string length are equal and takes three operands. equal and takes three operands. Packed decimal instructions Packed decimal instructions -A conventional set of arithmetic instructions is provided. -A conventional set of arithmetic instructions is provided. -The arithmetic shift and round instruction provides decimal point -The arithmetic shift and round instruction provides decimal point scaling and rounding. scaling and rounding.

16. MEMORY MAPPING -The 4.3GB virtual address space is divided into four regions. -The 4.3GB virtual address space is divided into four regions. -The first two regions-the program and control regions comprise -The first two regions-the program and control regions comprise the per process virtual address space which is uniquely mapped for the per process virtual address space which is uniquely mapped for each process. each process. -The second two regions-the system region and a region reserved for -The second two regions-the system region and a region reserved for future use-comprise the system virtual address space which is singly future use-comprise the system virtual address space which is singly mapped for all processes. mapped for all processes. -The program region contains user programs and data. -The program region contains user programs and data. -The control region contains operating system data structures specific -The control region contains operating system data structures specific to the process. to the process. -The system region contains procedures which are common to all -The system region contains procedures which are common to all processes. processes.

17. PROGRAM PROGRAM REGION REGION CONTROL CONTROL REGION REGION SYSTEM SYSTEM REGION REGION RESERVED FOR RESERVED FOR FUTURE EXPANSION VIRTUAL ADDRESS SPACE 1GB 1GB 2GB 2GB 3GB 3GB 4GB 4GB

18. PHYSICAL ADDRESS VIRTUAL ADDRESS VIRTUAL ADDRESS 313029 9 8 0  -------------------------------------VIRTUAL PAGE NUMBER-----------------------------------------------  ------BYTE WITHIN PAGE-------   -------------------------------------VIRTUAL PAGE NUMBER-----------------------------------------------  ------BYTE WITHIN PAGE-------  31 30 29 9 8 0 31 30 29 9 8 0  ------------------------------------PAGE FRAME NUMBER---------------------------------------------------  ------BYTE WITHIN PAGE---------   ------------------------------------PAGE FRAME NUMBER---------------------------------------------------  ------BYTE WITHIN PAGE--------- 

19. ACCESS CONTROL ACCESS CONTROL At a given point in time a process is in any of the four access At a given point in time a process is in any of the four access modes. modes. Kernel Kernel -Interrupt and exception handling, scheduling, paging, -Interrupt and exception handling, scheduling, paging, physical I/O, etc. physical I/O, etc. Executive Executive -Logical I/O as provided by RMS. -Logical I/O as provided by RMS. Supervisor Supervisor -The command interpreter. -The command interpreter. User User -User procedures and data. -User procedures and data.

20. Interrupts and Exceptions -VAX-11 provides a 31 priority level interrupt system. -VAX-11 provides a 31 priority level interrupt system. -16 levels(16-31) are provided for hardware. -16 levels(16-31) are provided for hardware. -15 levels(1-15) are provided for software. -15 levels(1-15) are provided for software. -current interrupt priority level (IPL) is stored in PSL. -current interrupt priority level (IPL) is stored in PSL. -interrupts are serviced by routines executing with kernel mode -interrupts are serviced by routines executing with kernel mode access control. access control. Process context switching Process context switching -The process context is gathered together in a data structure called a -The process context is gathered together in a data structure called a Process Control Block (PCB). Process Control Block (PCB). -while the process is executing, the process context resides in processor registers. -while the process is executing, the process context resides in processor registers. when switching from one process to another the process context from the when switching from one process to another the process context from the previously executing process is saved in its PCB in memory and the process previously executing process is saved in its PCB in memory and the process context for the process to be executed is loaded from it’s PCB in memory. context for the process to be executed is loaded from it’s PCB in memory.

21. VAX-11/780 IMPLEMENTATION -The vax-11/780 system is the first implementation -The vax-11/780 system is the first implementation of the VAX-11 architecture. When executed in of the VAX-11 architecture. When executed in compatibility mode vax-11/780 has a performance compatibility mode vax-11/780 has a performance comparable to PDP-11/70. comparable to PDP-11/70. - The VAX-11/780 system consists of - The VAX-11/780 system consists of CPU CPU - CPU implements the native and compatibility mode instructions - CPU implements the native and compatibility mode instructions sets, the memory management, and the interrupt and exception sets, the memory management, and the interrupt and exception mechanisms. mechanisms.

22. -CPU includes an 8KB byte write through cache or buffer memory (reduces the effective memory access time). -CPU includes an 8KB byte write through cache or buffer memory (reduces the effective memory access time). -To reduce delays CPU includes a write buffer. The CPU -To reduce delays CPU includes a write buffer. The CPU issues write to buffer and the actual memory write issues write to buffer and the actual memory write takes place in parallel with other CPU activity. takes place in parallel with other CPU activity. -Contains 128 entry address translation buffer which is -Contains 128 entry address translation buffer which is cache of recent virtual to physical translations. The buffer is divided cache of recent virtual to physical translations. The buffer is divided into two 64 entry sections: one for per process region and other for into two 64 entry sections: one for per process region and other for system region. system region. -Fourth buffer of CPU is 8-byte instruction buffer. It serves for two -Fourth buffer of CPU is 8-byte instruction buffer. It serves for two purposes. First, it decomposes the highly variable instruction purposes. First, it decomposes the highly variable instruction format into its basic components and second it also fetches ahead to reduce delays in obtaining instruction components. format into its basic components and second it also fetches ahead to reduce delays in obtaining instruction components.

23. -There is a writable diagnostic control store (WDCS) which is used for diagnostic purposes, implementation of certain instructions and for future -There is a writable diagnostic control store (WDCS) which is used for diagnostic purposes, implementation of certain instructions and for future micro code changes. micro code changes. SBI ( Synchronous Backplane Interconnect) -The SBI is the primary control and data transfer path in the VAX-11/780 -The SBI is the primary control and data transfer path in the VAX-11/780 system. system. -SBI is a synchronous bus with a cycle time of 200 nsec cycle. -SBI is a synchronous bus with a cycle time of 200 nsec cycle. -The data path width of the SBI is 32 bits. i.e during each 200 nsec cycle either 32 bits of data or a 30 bit physical address is transferred. -The data path width of the SBI is 32 bits. i.e during each 200 nsec cycle either 32 bits of data or a 30 bit physical address is transferred. -Arbitration of SBI is distributed :each interface to the SBI has a specific priority and its own bus request line. when interface wishes to use the bus, -Arbitration of SBI is distributed :each interface to the SBI has a specific priority and its own bus request line. when interface wishes to use the bus, it asserts its bus request line. If at the end of 200 nsec cycle there are no interfaces of higher priority requesting the bus, the interface takes control of the bus. it asserts its bus request line. If at the end of 200 nsec cycle there are no interfaces of higher priority requesting the bus, the interface takes control of the bus.

24. Memory subsystem -The memory subsystem consists of one or two memory controllers -The memory subsystem consists of one or two memory controllers with up to 1 MB of memory on each. The memory is organized in 64 bit with up to 1 MB of memory on each. The memory is organized in 64 bit quadwords with an 8-bit ECC which provides single bit error correction and double bit error detection. quadwords with an 8-bit ECC which provides single bit error correction and double bit error detection. -The memory controllers have buffers which hold up to four memory requests. These buffers substantially increase the utilization of the SBI and -The memory controllers have buffers which hold up to four memory requests. These buffers substantially increase the utilization of the SBI and memory by permitting the pipelining of multiple memory requests. memory by permitting the pipelining of multiple memory requests.

25. I/O subsystem -The I/O subsystem consists of buffered interfaces or adapters between -The I/O subsystem consists of buffered interfaces or adapters between the SBI and the two types of peripheral buses: Unibus and Massbus. the SBI and the two types of peripheral buses: Unibus and Massbus. -The Unibus is a medium speed multiplexor bus which is used as primary -The Unibus is a medium speed multiplexor bus which is used as primary memory as well as peripheral bus. memory as well as peripheral bus. -Unibus has an 18-bit physical address space and supports byte and word transfers. -Unibus has an 18-bit physical address space and supports byte and word transfers. -The Massbus is a high speed block transfer bus used primarily for disks and -The Massbus is a high speed block transfer bus used primarily for disks and tapes. tapes.

26. VAX-11/780

27. Thank You Thank You