1. Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

3. Direct Memory Access Module MTT48 10 - 3 M Module Objective By the end of this module, you should be able to: Configure the DMA Service TIM, SPI and SCI interrupts via DMA Initiate DMA block data transfers Module Exercise: Service TIM channel output compare via DMA Service SPI transmission complete via DMA Service SCI received data via DMA Initiate block data moves

4. Direct Memory Access Module MTT48 10 - 4 M DIRECT MEMORY ACCESS (DMA) MODULE 68HC08 CPU System Integration Module (SIM) Clock Generation Module (CGM) Timer Interface Module (TIM) Direct Memory Access Module (DMA) Serial Communications Interface (SCI) Internal Bus (IBUS) Serial Peripheral Interface (SPI) Random Access Memory (RAM) Electronically Programmable Memory (EPROM) LVI COP Monitor ROM IRQ BREAK RESET Modular Architecture Service Request-Driven Operation Without CPU Intervention Three Independent Channels Byte or Word Transfer Capability Block Transfers and Loop Transfers CPU Interrupt Capability on Completion of Block Transfer or on Loop Restart Programmable DMA Bus Bandwidth (25%, 50%, 67%, or 100% of Total Bus Bandwidth) Programmable DMA Service Request/CPU Interrupt Request Priority Programmable DMA Enable during Wait Mode Block Transfers Up to 256 Bytes Expandable Architecture Up to Seven Channels and Eight Transfer Source Inputs

5. Direct Memory Access Module MTT48 10 - 5 M DMA Block Diagram ALU 70 7 7 0 0 SYSTEM CONTROL LOGIC 15 15 0 0 = BUS SWITCH CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 0 CHANNEL 1 CHANNEL 2 DESTINATION ADDRESS REGISTERS SOURCE ADDRESS REGISTERS CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 0 CHANNEL 1 CHANNEL 2 BYTE COUNT REGISTERS BLOCK LENGTH REGISTERS CHANNEL CONTROL REGISTERS INTERNAL BUS

6. Direct Memory Access Module MTT48 10 - 6 M BUS Bandwidth & Interface DMA uses same address/data lines as the CPU Small data transfers have little CPU impact Large data transfers will slow CPU activity –Control DMA/CPU bandwidth ratio –Select 25, 50, 67 or 100% DMA/CPU bus bandwidth DMA interface Controls the R/W line, address bus and data bus CPU resumes control when DMA completes Bus cycles –requires 2 cycles to transfer an 8 bit byte –requires 4 cycles to transfer a 16 bit word ADDRESS CGMOUT BUS DATA BUS DMA (src)DMA (dest) DMA (read)DMA (write) CPU

7. Direct Memory Access Module MTT48 10 - 7 M Address Calculations DMA arithmetic/logic unit (ALU) responsibilities: Calculates transfer source and destination addresses –May increment, decrement or remain static Increments byte count register Determines if transfer is complete –Stops transfer after a fixed number of bytes transfer –Begins transfer again ( looping )

8. Direct Memory Access Module MTT48 10 - 8 M Example Calculation 1 Source and destination address configured as increment do Repeat Source Address = Source Base Address + Byte Count Destination Address = Destination Base Address + Byte Count Add 1 to Byte Count Until Byte Count = Block Length Set transfer complete flag If interrupt enabled, then generate interrupt request Set Byte Count = 0 While Looping Enabled Clear Channel Transfer Enable Bit

9. Direct Memory Access Module MTT48 10 - 9 M Example Calculation 2 Source address configured as decrement Destination address configured as static do Repeat Source Address = Source Base Address - Byte Count Destination Address = Destination Base Address Add 1 to Byte Count Until Byte Count = Block Length Set transfer complete flag If interrupt enabled then generate interrupt request Set Byte Count = 0 While Looping Enabled Clear Channel Transfer Enable Bit

10. Direct Memory Access Module MTT48 10 - 10 M DMA I/O Registers Control and monitor registers DMA Control register (DC1) DMA Status and Control register (DSC) DMA Control register 2 (DC2) Channel operation registers DMA channel Source address registers (DxSH:DxSL) DMA channel destination address registers (DxDH:DxDL) DMA channel control registers (D0C - D2C) DMA channel byte count registers (D0BC - D2BC) DMA channel block length registers (D0BL - D2BL)

11. Direct Memory Access Module MTT48 10 - 11 M DMA Control DMA Control register 1 (DC1) Bus Bandwidth Control (BB1, BB0) –Controls the ratio of DMA/CPU bus activity Transfer enable (TECx) –Enables a channel to access address and data bus upon DMA triggering 1 = DMA channel x enabled 0 = DMA channel x disabled CPU Interrupt enable (IECx) –Enables CPU interrupt upon transfer completion or restart of DMA transfer loop 1 = DMA channel x interrupts enabled 0 = DMA channel x interrupts disabled RESET:0 0 0 0 00 0 0 WRITE: READ: DC1 BB1 BB0 TEC2 IEC2 TEC1 IEC1 TEC0 IEC0 BB1:BB0 DMA Bus Cycles 00 01 10 11 CPU Bus Cycles 25%75% 50% 0% 67% 33% 100%

12. Direct Memory Access Module MTT48 10 - 12 M DMA Status and Control Register DMA Status and Control register 1 (DSC) Channel Status flags (IFCx) –Indicate DMA loop or transfer has completed –Generates a CPU interrupt ( if IECx is enabled ) –Cleared by reading then writing logic 0 to flag bit 1 = DMA transfer complete 0 = DMA transfer not complete DMA Loop enable bits (L2 -L0) –Enables looping back to the base addresses and repeating transfer again –Continues looping until disabled 1 = Loop mode enabled 0 = Loop mode disabled RESET:0 0 0 0 00 0 0 WRITE: READ: DSC DMAP L2 L1L0 DMAWE IFC2 IFC1 IFC0

13. Direct Memory Access Module MTT48 10 - 13 M RESET:0 0 0 0 00 0 0 WRITE: READ: DSC DMAP L2 L1L0 DMAWE IFC2 IFC1 IFC0 DMA Status and Control register (DSC) DMA Priority (DMAP) –Controls the priority of DMA module interrupts DMA Wait Enable (DMAWE) –Enables DMA to operate while CPU in WAIT mode 1 = DMA enabled during WAIT instruction 0 = DMA suspended DMAP = 0DMAP = 1 ResetReset Software Interrupt (SWI)DMA Channel 0 Interrupt External InterruptDMA Channel 1 Interrupt Timer InterruptDMA Channel 2 Interrupt SPI InterruptSoftware Interrupt (SWI) SCI InterruptExternal Interrupt DMA Channel 0 InterruptTimer Interrupt DMA Channel 1 InterruptSPI Interrupt DMA Channel 2 InterruptSCI Interrupt Highest Priority Lowest Priority DMA Status and Control Register

14. Direct Memory Access Module MTT48 10 - 14 M Interrupts DMAP = 1 –Lower priority CPU interrupts recognized after current DMA transfer completes –Block Transfers CPU Interrupt latency depends on size and bandwidth bits DMAP = 0 –Higher priority CPU interrupts recognized after current byte is transferred –Clears the transfer enable bit (TECx) Software must reenable the DMA channels DMA Priority

15. Direct Memory Access Module MTT48 10 - 15 M Address Control, Transfer Data Size, & Source Selection DMA Channel Control register 1 (D0C - D2C) Source/Destination address control (SDC3 - SDC0) –Control calculation of source/destination addresses –Assignments are implementation specific RESET:INDETERMINATE AFTER RESET x = 0, 1 or 2 WRITE: READ: DxC SDC3 SDC2 SDC1SDC0 BWC DTS2 DTS1 DTS0 SDC3:SDC2:SDC1:SDC0 1010 1001 1000 Source Address Destination Address Increment 0110 0101 0100 0010 0001 0000 Increment Decrement Increment Decrement Increment Static Increment Decrement Static Decrement Transfer Source TIM Channel 0 Interrupt Request TIM Channel 1Interrupt Request TIM Channel 2 Interrupt Request TIM Channel 3 Interrupt Request SPI Transmit Interrupt Request SPI Receive Interrupt Request SCI Receive Interrupt Request SCI Transmit Interrupt Request DTS2:DTS1:DTS0 000 001 010 011 100 101 110 111 Byte/Word control (BWC) Selects 8-bit byte or 16-bit word transfers –Source and/or Destination address must be static or BWC has no effect –Designed for 16 bit register transfer 1 = 16-bit words 0 = 8-bit bytes DMA Transfer source bits (DTS2 -DTS0) –Assigns the DMA channel to a source input

16. Direct Memory Access Module MTT48 10 - 16 M Source Address Registers DMA Source Address Registers (D0SH/L - D2SH/L) Contains the source base address Used as base pointers during transfer calculations WRITE: READ: DxSH AD15 AD14 AD13AD12 AD11 AD10 AD9 AD8 RESET:INDETERMINATE AFTER RESET WRITE: READ: DxSL AD7 AD6 AD5AD4 AD3 AD2 AD1 AD0 WRITE: READ: DxDH AD15 AD14 AD13AD12 AD11 AD10 AD9 AD8 RESET:INDETERMINATE AFTER RESET WRITE: READ: DxDL AD7 AD6 AD5AD4 AD3 AD2 AD1 AD0 DMA Destination Address Registers (D0DH/L - D2DH/L) Contains the destination base address Used as base pointers during transfer calculations Destination Address Registers

17. Direct Memory Access Module MTT48 10 - 17 M Block Length Registers DMA Block Length registers (D0BL - D2BL) Contains number of bytes to transfer Compared to Byte Count register –Determines if transfer is complete RESET:INDETERMINATE AFTER RESET WRITE: READ: DxBL BL7 BL6 BL5BL4 BL3 BL2 BL1 BL0 Byte Count Registers DMA Byte Count registers (D0BC - D2BC) Contains the number of bytes transferred on that channel Compared to Block Length register –Determines if transfer is complete Cleared when: –Block Length = Byte Count –Write to the Channel source address register –Write to the Channel destination address register RESET:00000000 WRITE: READ: DxBC BC7 BC6 BC5BC4 BC3 BC2 BC1 BC0

18. Direct Memory Access Module MTT48 10 - 18 M DMA Setup 1) Write initial source address to source address register 2) Write initial destination address to destination address register 3) Select address manipulation for source/destination addresses, data size and transfer source (DxC) 4) Enter number of bytes to transfer(DxBL) 5) Enable interrupts (if desired), select the bandwidth (DC1) 6) Enable the channel (DC1) 7) To force transfer: set SWIx (DC2) Note: Not necessary for normal DMA transfer

19. Direct Memory Access Module MTT48 10 - 19 M DMA Exercise Part 1 Write a code sequence to configure DMA channel 0 to service a TIM channel 0 interrupt. The DMA will write a new output compare value from location $50 and $51 to TCH0H:TCH0L register. Part 2 Configure DMA channel 1 to service SPI transmission complete interrupt. The DMA will read the SPI data register and store the data at location $52. Part 3 Have DMA channel 2 service SCI data received interrupts. The DMA will read the SCI data register and store the data at location $53. Given: TCH0EQU$0027;Timer channel 0 register SPDREQU$0012;SPI data register SCDREQU$0018;SCI data register

20. Direct Memory Access Module MTT48 10 - 20 M Force Transfer DMA Control register 2 (DC2) Initiates DMA transfers Simulates interrupts for test purposes Software initiated (SWI7 -SWI0) –Assignments are implementation specific –Initiates DMA request from DMA transfer source –Selected channel must be enabled for transfer to begin –Channel must have transfer source input (DTSx) assigned 1 = DMA software transfer initiated 0 = DMA software transfer halted RESET:00000000 WRITE: READ: DC2 SWI7 SWI6 SWI5SWI4 SWI3 SWI2 SWI1 SWI0

21. Direct Memory Access Module MTT48 10 - 21 M Exercise Part 4 Write a code sequence that configures DMA channel 0 to initialize 176 bytes of RAM (the rest of page 0 RAM) to 0 starting at address $50. This routine should signal the CPU when complete. Since this is a large transfer, consider using 25 to 50% bus bandwidth. Note: Set location $50 to zero first, then use this as the source location.

22. Direct Memory Access Module MTT48 10 - 22 M Low Power Modes WAIT IF DMAWE is set: –DMA will complete transfers –Will execute transfers on all DMA interrupt requests –Can generate interrupt source that wakes CPU If DMAWE is clear: –Suspends DMA transfers, resumes after Wait terminates STOP Suspends DMA transfer Upon STOP termination: –Reset aborts DMA transfer –External interrupt will resume DMA transfer

23. Direct Memory Access Module MTT48 10 - 23 M RESET:0 0 0 0 00 0 0 WRITE: READ: DC1 BB1 BB0 TEC2 IEC2 TEC1 IEC1 TEC0 IEC0 RESET:0 0 0 0 00 0 0 WRITE: READ: DSC DMAP L2 L1L0 DMAWE IFC2 IFC1 IFC0 RESET:INDETERMINATE AFTER RESET x = 0, 1 or 2 WRITE: READ: DxC SDC3 SDC2 SDC1SDC0 BWC DTS2 DTS1 DTS0 WRITE: READ: DxSH AD15 AD14 AD13AD12 AD11 AD10 AD9 AD8 RESET:INDETERMINATE AFTER RESET WRITE: READ: DxSL AD7 AD6 AD5AD4 AD3 AD2 AD1 AD0 DMA Register Summary

24. Direct Memory Access Module MTT48 10 - 24 M WRITE: READ: DxDH AD15 AD14 AD13AD12 AD11 AD10 AD9 AD8 RESET:INDETERMINATE AFTER RESET WRITE: READ: DxDL AD7 AD6 AD5AD4 AD3 AD2 AD1 AD0 RESET:INDETERMINATE AFTER RESET WRITE: READ: DxBL BL7 BL6 BL5BL4 BL3 BL2 BL1 BL0 RESET:00000000 WRITE: READ: DxBC BC7 BC6 BC5BC4 BC3 BC2 BC1 BC0 RESET:00000000 WRITE: READ: DC2 SWI7 SWI6 SWI5SWI4 SWI3 SWI2 SWI1 SWI0 DMA Register Summary Continued

25. Direct Memory Access Module MTT48 10 - 25 M Exercise Solution - part 1 - ; DMA exercise - all registers have been predefined with equates ; Part 1 ORG$0050 Data1RMB2 ORG$7000 CLRD0SH; set up source address (high byte) MOV#Data1, D0SL; set up source address (low byte) MOV#TCH0H, D0DH; set up dest. address (high byte) MOV#TCH0L, D0DL; set up dest. address (low byte) MOV#$08, D0C; select TIM 0, word length ; static source and destination MOV#$02, D0BL; move 2 bytes MOV#$00, DSC; normal priority, Suspend during Wait MOV#$02, DC1; 100% Bandwidth, Enable channel 0 ; interrupt generation turned off MOV#$02, DC1; enable channel 0

26. Direct Memory Access Module MTT48 10 - 26 M Exercise Solution - part 2 - ; DMA exercise - all registers have been predefined with equates ; Part 2 ORG$0052 Data2RMB1 CLRD1SH; SPI is source address MOV#SPDR, D1SL; CLRD1DH; Data is the destination address MOV#Data2, D1DL; MOV#$04, D1C; Select SPI, byte length ; Static source and destination MOV#$01, D1BL; Move 1 byte LDADC1; Read current register value ORA#$08 STADC1; enable channel 1

27. Direct Memory Access Module MTT48 10 - 27 M Exercise Solution - part 3 - ; DMA exercise ; Part 3 ORG$0053 Data3RMB1 CLRD2SH; set up source source address (low byte) CLRD2DH; set up dest. address (high byte) MOV#Data3, D2DL; set up dest. address (low byte) MOV#$06, D2C; select SCI, byte length ; static source and destination MOV#$01, D2BL; move 1 byte LDADC1; Read current register value ORA#$20 STADC1; enable channel 2

28. Direct Memory Access Module MTT48 10 - 28 M ; DMA exercise ; Part 4 StartEQU$50 ORG$7000 CLRStart CLRD0SH MOV#Start,D0SL; Set up source address CLRD0DH MOV#Start,D0DL; set up dest. address MOV#$23,D0C; select TIM 3 - unused, byte size ; static source and incr. destination MOV#176,D0BL; move 176 bytes MOV#$00,DSC; normal priority, Suspend during Wait MOV#$43,DC1; 50% Bandwidth, Enable channel 0, ; enable interrupt MOV#$08,DC2; Start block transfer by forcing interrupt Exercise Solution - part 4 -